A 1.56mW 50MHz 3rd-order filter with current-mode active-RC biquad and 33dBm IIP3 in 65nm CMOS

Rakesh Kumar Palani, Martin Sturm, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

A novel inverter-based-integrator filter design is proposed that relaxes the UGB requirement of the OTAs by decoupling the integration capacitance from the feedback loop. The proposed scheme allows the entire filtering operation to take place in the current domain reducing power supply limitations. Further, in the design the load acts as the compensation capacitance to the OTAs allowing the majority of the current to flow into the load, increasing the overall power efficiency. As a proof of concept, a 3rd order lowpass filter is designed and implemented in an IBM 65nm CMOS process. The measured prototype designed for a 50MHz bandwidth achieves an IIP3 of +33dBm and 1.8X better FOM over state-of-art while drawing 1.3mA from a 1.2V supply, is capable of driving a lpF load, and occupies 6X smaller area.

Original languageEnglish (US)
Title of host publicationProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages373-376
Number of pages4
DOIs
StatePublished - Dec 1 2013
Event2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
Duration: Nov 11 2013Nov 13 2013

Publication series

NameProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Other

Other2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Country/TerritorySingapore
CitySingapore
Period11/11/1311/13/13

Keywords

  • Active filters
  • Active-RC
  • Biquad
  • Butterworth
  • Current-mode
  • Filters
  • Gm-C
  • Integrator
  • Lowpass

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