A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording

Anh Tuan Nguyen; Jian Xu; Zhi Yang

doi:10.1109/CICC.2015.7338460

A 14-bit 0.17mm² SAR ADC in 0.13μm CMOS for high precision nerve recording

Anh Tuan Nguyen
, Jian Xu
, Zhi Yang

Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new "half-split" feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm² (280μmx620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.

Original language	English (US)
Title of host publication	2015 IEEE Custom Integrated Circuits Conference, CICC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479986828
DOIs	https://doi.org/10.1109/CICC.2015.7338460
State	Published - Nov 25 2015
Event	IEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States Duration: Sep 28 2015 → Sep 30 2015

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2015-November
ISSN (Print)	0886-5930

Other

Other	IEEE Custom Integrated Circuits Conference, CICC 2015
Country/Territory	United States
City	San Jose
Period	9/28/15 → 9/30/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

High-resolution SAR ADC
capacitor mismatches estimation and calibration
half-split DAC array
high precision nerve recording

Publisher link

10.1109/CICC.2015.7338460

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Cite this

Nguyen, A. T., Xu, J., & Yang, Z. (2015). A 14-bit 0.17mm² SAR ADC in 0.13μm CMOS for high precision nerve recording. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015 Article 7338460 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2015.7338460

A 14-bit 0.17mm² SAR ADC in 0.13μm CMOS for high precision nerve recording. / Nguyen, Anh Tuan; Xu, Jian; Yang, Zhi.
2015 IEEE Custom Integrated Circuits Conference, CICC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7338460 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nguyen, AT, Xu, J & Yang, Z 2015, A 14-bit 0.17mm² SAR ADC in 0.13μm CMOS for high precision nerve recording. in 2015 IEEE Custom Integrated Circuits Conference, CICC 2015., 7338460, Proceedings of the Custom Integrated Circuits Conference, vol. 2015-November, Institute of Electrical and Electronics Engineers Inc., IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, United States, 9/28/15. https://doi.org/10.1109/CICC.2015.7338460

@inproceedings{7b5f97f965714a8d8161d6b0fed6b4f0,

title = "A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording",

abstract = "This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new {"}half-split{"} feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μmx620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.",

keywords = "High-resolution SAR ADC, capacitor mismatches estimation and calibration, half-split DAC array, high precision nerve recording",

author = "Nguyen, \{Anh Tuan\} and Jian Xu and Zhi Yang",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE Custom Integrated Circuits Conference, CICC 2015 ; Conference date: 28-09-2015 Through 30-09-2015",

year = "2015",

month = nov,

day = "25",

doi = "10.1109/CICC.2015.7338460",

language = "English (US)",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE Custom Integrated Circuits Conference, CICC 2015",

}

TY - GEN

T1 - A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording

AU - Nguyen, Anh Tuan

AU - Xu, Jian

AU - Yang, Zhi

PY - 2015/11/25

Y1 - 2015/11/25

N2 - This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new "half-split" feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μmx620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.

AB - This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new "half-split" feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μmx620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.

KW - High-resolution SAR ADC

KW - capacitor mismatches estimation and calibration

KW - half-split DAC array

KW - high precision nerve recording

UR - https://www.scopus.com/pages/publications/84959232165

UR - https://www.scopus.com/pages/publications/84959232165#tab=citedBy

U2 - 10.1109/CICC.2015.7338460

DO - 10.1109/CICC.2015.7338460

M3 - Conference contribution

AN - SCOPUS:84959232165

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - 2015 IEEE Custom Integrated Circuits Conference, CICC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Custom Integrated Circuits Conference, CICC 2015

Y2 - 28 September 2015 through 30 September 2015

ER -