A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Ki Chul Chun; Pulkit Jain; Tae Ho Kim; Chris H. Kim

doi:10.1109/VLSIC.2010.5560303

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Ki Chul Chun
, Pulkit Jain
, Tae Ho Kim
, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Scopus citations

Abstract

A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

Original language	English (US)
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	191-192
Number of pages	2
ISBN (Print)	9781424476367
DOIs	https://doi.org/10.1109/VLSIC.2010.5560303
State	Published - 2010
Event	24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, United States Duration: Jun 16 2010 → Jun 18 2010

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Conference

Conference	24th Symposium on VLSI Circuits, VLSIC 2010
Country/Territory	United States
City	Honolulu
Period	6/16/10 → 6/18/10

Publisher link

10.1109/VLSIC.2010.5560303

Find It

Find It at U of M Libraries

Cite this

Chun, K. C., Jain, P., Kim, T. H., & Kim, C. H. (2010). A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec. In 2010 Symposium on VLSI Circuits, VLSIC 2010 (pp. 191-192). Article 5560303 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2010.5560303

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec. / Chun, Ki Chul; Jain, Pulkit; Kim, Tae Ho et al.
2010 Symposium on VLSI Circuits, VLSIC 2010. Institute of Electrical and Electronics Engineers Inc., 2010. p. 191-192 5560303 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chun, KC, Jain, P, Kim, TH & Kim, CH 2010, A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec. in 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560303, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 191-192, 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, United States, 6/16/10. https://doi.org/10.1109/VLSIC.2010.5560303

Chun KC, Jain P, Kim TH, Kim CH. A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec. In 2010 Symposium on VLSI Circuits, VLSIC 2010. Institute of Electrical and Electronics Engineers Inc. 2010. p. 191-192. 5560303. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2010.5560303

@inproceedings{298a065a0f1b4d21bffdd0b234ca2412,

title = "A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec",

abstract = "A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9\% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.",

author = "Chun, \{Ki Chul\} and Pulkit Jain and Kim, \{Tae Ho\} and Kim, \{Chris H.\}",

year = "2010",

doi = "10.1109/VLSIC.2010.5560303",

language = "English (US)",

isbn = "9781424476367",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "191--192",

booktitle = "2010 Symposium on VLSI Circuits, VLSIC 2010",

note = "24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",

}

TY - GEN

T1 - A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

AU - Chun, Ki Chul

AU - Jain, Pulkit

AU - Kim, Tae Ho

AU - Kim, Chris H.

PY - 2010

Y1 - 2010

N2 - A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

AB - A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

UR - https://www.scopus.com/pages/publications/77958002044

UR - https://www.scopus.com/pages/publications/77958002044#tab=citedBy

U2 - 10.1109/VLSIC.2010.5560303

DO - 10.1109/VLSIC.2010.5560303

M3 - Conference contribution

AN - SCOPUS:77958002044

SN - 9781424476367

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 191

EP - 192

BT - 2010 Symposium on VLSI Circuits, VLSIC 2010

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Symposium on VLSI Circuits, VLSIC 2010

Y2 - 16 June 2010 through 18 June 2010

ER -

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Abstract

Publication series

Conference

Publisher link

Find It

Other files and links

Fingerprint

Cite this