A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Ki Chul Chun, Pulkit Jain, Tae Ho Kim, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

Original languageEnglish (US)
Title of host publication2010 Symposium on VLSI Circuits, VLSIC 2010
Pages191-192
Number of pages2
DOIs
StatePublished - Oct 22 2010
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: Jun 16 2010Jun 18 2010

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
CountryUnited States
CityHonolulu, HI
Period6/16/106/18/10

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