A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer

Po-wei Chiu; Somnath Kundu; Qianying Tang; Chris H. Kim

doi:10.23919/VLSIC.2017.8008546

A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer

Po-wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10^-12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ BER monitor.

Original language	English (US)
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C56-C57
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008546
State	Published - Aug 10 2017
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: Jun 5 2017 → Jun 8 2017

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/Territory	Japan
City	Kyoto
Period	6/5/17 → 6/8/17

Bibliographical note

Publisher Copyright:
© 2017 JSAP.

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.23919/VLSIC.2017.8008546

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Chiu, P., Kundu, S., Tang, Q., & Kim, C. H. (2017). A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C56-C57). Article 8008546 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008546

A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer. / Chiu, Po-wei; Kundu, Somnath; Tang, Qianying et al.
2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C56-C57 8008546 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chiu, P, Kundu, S, Tang, Q & Kim, CH 2017, A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008546, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C56-C57, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 6/5/17. https://doi.org/10.23919/VLSIC.2017.8008546

Chiu P, Kundu S, Tang Q, Kim CH. A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C56-C57. 8008546. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2017.8008546

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A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer

Abstract

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