A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer

Po-wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

An all-digital 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was demonstrated on a 10mm on-chip serial link. Implemented in a 65nm GP technology, the transmitter and receiver achieve an energy-efficiency of 31.9 and 45.3 fJ/b/mm, respectively, at a data rate of 10Gb/s. A Bit Error Rate (BER) less than 10-12 was verified for an eye width of 0.43 Unit Interval (UI) using an in-situ BER monitor.

Original languageEnglish (US)
Title of host publication2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC56-C57
ISBN (Electronic)9784863486065
DOIs
StatePublished - Aug 10 2017
Event31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan
Duration: Jun 5 2017Jun 8 2017

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other31st Symposium on VLSI Circuits, VLSI Circuits 2017
CountryJapan
CityKyoto
Period6/5/176/8/17

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    Chiu, P., Kundu, S., Tang, Q., & Kim, C. H. (2017). A 10Gb/s 10mm on-chip serial link in 65nm CMOS featuring a half-rate time-based decision feedback equalizer. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C56-C57). [8008546] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008546