Abstract
A smart wearable electrocardiographic (ECG) processor is presented for secure ECG-based biometric authentication and cardiac monitoring, including arrhythmia and anomaly detection. Data-driven Lasso regression and low-precision techniques are developed to compress the neural networks by 24.4X. The prototype chip fabricated in 65 nm LP CMOS consumes 1.06 μW at 0.55 V for real-time ECG authentication. Equal error rates of 0.74% and 1.7% are achieved on ECG-ID database and in-house 645-subject database, respectively.
Original language | English (US) |
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Title of host publication | 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | C102-C103 |
ISBN (Electronic) | 9784863486065 |
DOIs | |
State | Published - Aug 10 2017 |
Externally published | Yes |
Event | 31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: Jun 5 2017 → Jun 8 2017 |
Publication series
Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Other
Other | 31st Symposium on VLSI Circuits, VLSI Circuits 2017 |
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Country/Territory | Japan |
City | Kyoto |
Period | 6/5/17 → 6/8/17 |
Bibliographical note
Publisher Copyright:© 2017 JSAP.