As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low power solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, Dynamic Threshold Error Correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65nmLP CMOS we achieve, to our knowledge, the lowest reported energy efficiency for a neuromorphic processor with 52.4TSOp/s/W (104.8TOp/S/W) at 0.7V with 3b resolution for an impressive 19.1fJ/MAC.
|Original language||English (US)|
|Title of host publication||2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Dec 14 2018|
|Event||2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China|
Duration: Nov 5 2018 → Nov 7 2018
|Name||2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings|
|Other||2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018|
|Country||Taiwan, Province of China|
|Period||11/5/18 → 11/7/18|
Bibliographical noteFunding Information:
This research was supported in part by the National Science Foundation under award number CCF-1763761 and IGERT grant DGE-1069104.