A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm

Luke R. Everson; Muqing Liu; Nakul Pande; Chris H. Kim

doi:10.1109/ASSCC.2018.8579302

A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm

Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low power solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, Dynamic Threshold Error Correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65nmLP CMOS we achieve, to our knowledge, the lowest reported energy efficiency for a neuromorphic processor with 52.4TSOp/s/W (104.8TOp/S/W) at 0.7V with 3b resolution for an impressive 19.1fJ/MAC.

Original language	English (US)
Title of host publication	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	273-276
Number of pages	4
ISBN (Electronic)	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579302
State	Published - Dec 14 2018
Event	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China Duration: Nov 5 2018 → Nov 7 2018

Publication series

Name	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Other

Other	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/Territory	Taiwan, Province of China
City	Tainan
Period	11/5/18 → 11/7/18

Bibliographical note

Funding Information:
This research was supported in part by the National Science Foundation under award number CCF-1763761 and IGERT grant DGE-1069104.

Publisher Copyright:
© 2018 IEEE.

Publisher link

10.1109/ASSCC.2018.8579302

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Everson, L. R., Liu, M., Pande, N., & Kim, C. H. (2018). A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 273-276). Article 8579302 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579302

A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. / Everson, Luke R.; Liu, Muqing; Pande, Nakul et al.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 273-276 8579302 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Everson, LR, Liu, M, Pande, N & Kim, CH 2018, A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579302, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 273-276, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 11/5/18. https://doi.org/10.1109/ASSCC.2018.8579302

Everson LR, Liu M, Pande N, Kim CH. A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 273-276. 8579302. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579302

Everson, Luke R. ; Liu, Muqing ; Pande, Nakul et al. / A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 273-276 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

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abstract = "As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low power solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, Dynamic Threshold Error Correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65nmLP CMOS we achieve, to our knowledge, the lowest reported energy efficiency for a neuromorphic processor with 52.4TSOp/s/W (104.8TOp/S/W) at 0.7V with 3b resolution for an impressive 19.1fJ/MAC.",

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note = "Funding Information: This research was supported in part by the National Science Foundation under award number CCF-1763761 and IGERT grant DGE-1069104. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",

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A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm

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