This paper presents a 100MS/s 9b companding SAR ADC which exploits the statistical properties of broadband multi-carrier signals to reduce the dynamic range requirement for the ADC. The architecture emulates the performance of a higher resolution ADC by reducing the PAPR of a multi-carrier signal to that of a single carrier. Additionally, gain-before-sampling results in reduced sampling capacitor size which lowers power and area. To verify the concept, a prototype implemented in TSMC's 65nm GP CMOS process consumes 12.27 mW at 100 MS/s while extending the dynamic range of the sub-ADC by 13 dB, and resulting in a Schreier FOM of 150.7 dB.
|Original language||English (US)|
|Title of host publication||2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Jan 22 2019|
|Event||61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada|
Duration: Aug 5 2018 → Aug 8 2018
|Name||Midwest Symposium on Circuits and Systems|
|Conference||61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018|
|Period||8/5/18 → 8/8/18|
Bibliographical noteFunding Information:
Research funded by DARPA CLASIC.
© 2018 IEEE