A 100MS/s 9-bit companding SAR ADC with on-chip input driver in 65nm CMOS for multi-carrier communications

Anindya Saha, Saurabh Chaubey, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 100MS/s 9b companding SAR ADC which exploits the statistical properties of broadband multi-carrier signals to reduce the dynamic range requirement for the ADC. The architecture emulates the performance of a higher resolution ADC by reducing the PAPR of a multi-carrier signal to that of a single carrier. Additionally, gain-before-sampling results in reduced sampling capacitor size which lowers power and area. To verify the concept, a prototype implemented in TSMC's 65nm GP CMOS process consumes 12.27 mW at 100 MS/s while extending the dynamic range of the sub-ADC by 13 dB, and resulting in a Schreier FOM of 150.7 dB.

Original languageEnglish (US)
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages174-177
Number of pages4
ISBN (Electronic)9781538673928
DOIs
StatePublished - Jan 22 2019
Event61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
Duration: Aug 5 2018Aug 8 2018

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2018-August
ISSN (Print)1548-3746

Conference

Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
CountryCanada
CityWindsor
Period8/5/188/8/18

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  • Cite this

    Saha, A., Chaubey, S., & Harjani, R. (2019). A 100MS/s 9-bit companding SAR ADC with on-chip input driver in 65nm CMOS for multi-carrier communications. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 (pp. 174-177). [8623873] (Midwest Symposium on Circuits and Systems; Vol. 2018-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2018.8623873