@inproceedings{7f64537d441a4912b8a3c8ac66f2a70a,
title = "A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit",
abstract = "A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent firstorder noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of -97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm2. The PLL circuit has an FoM of -226.7dB.",
author = "Bongjin Kim and Somnath Kundu and Kim, {Chris H.}",
year = "2015",
month = aug,
day = "31",
doi = "10.1109/VLSIC.2015.7231355",
language = "English (US)",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "C140--C141",
booktitle = "2015 Symposium on VLSI Circuits, VLSI Circuits 2015",
note = "29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 ; Conference date: 17-06-2015 Through 19-06-2015",
}