A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit

Bongjin Kim; Somnath Kundu; Chris H. Kim

doi:10.1109/VLSIC.2015.7231355

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit

Bongjin Kim, Somnath Kundu, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent firstorder noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of -97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm². The PLL circuit has an FoM of -226.7dB.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C140-C141
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231355
State	Published - Aug 31 2015
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: Jun 17 2015 → Jun 19 2015

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Other

Other	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	6/17/15 → 6/19/15

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10.1109/VLSIC.2015.7231355

Cite this

Kim, B., Kundu, S., & Kim, C. H. (2015). A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C140-C141). [7231355] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231355

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. / Kim, Bongjin; Kundu, Somnath; Kim, Chris H.

2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C140-C141 7231355 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, B, Kundu, S & Kim, CH 2015, A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231355, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C140-C141, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 6/17/15. https://doi.org/10.1109/VLSIC.2015.7231355

Kim B, Kundu S, Kim CH. A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C140-C141. 7231355. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2015.7231355

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title = "A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit",

abstract = "A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent firstorder noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of -97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm2. The PLL circuit has an FoM of -226.7dB.",

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AB - A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent firstorder noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of -97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm2. The PLL circuit has an FoM of -226.7dB.

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A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit

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