A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection

Naser Mousavi; Zhiheng Wang; Ramesh Harjani

doi:10.1109/ESSCIRC.2018.8494249

A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection

Naser Mousavi
, Zhiheng Wang
, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

An ultra-fast frequency hopping spread spectrum transceiver front-end architecture is presented that provides 20dB of processing gain at RF for the first time. This enables the receiver front-end to supress any in-band interferes by 20dB before they arrive at the LNA. The circuit consists of passive mixers and agile digital oscillator/DAC engines that are capable of quickly moving in the frequency domain with very low power. A transient hop time of 1.5ns is achieved in this design. The front-end implemented in 65nm CMOS technology, occupies an active area of 3.lmm², and consumes 24mW (=P_TX=P_RX) from a 1V power supply for a center frequency of 1GHz.

Original language	English (US)
Title of host publication	ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	246-249
Number of pages	4
ISBN (Electronic)	9781538654040
DOIs	https://doi.org/10.1109/ESSCIRC.2018.8494249
State	Published - Oct 16 2018
Event	44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 - Dresden, Germany Duration: Sep 3 2018 → Sep 6 2018

Publication series

Name	ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference

Other

Other	44th IEEE European Solid State Circuits Conference, ESSCIRC 2018
Country/Territory	Germany
City	Dresden
Period	9/3/18 → 9/6/18

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This research work was funded under the DARPA SPAR program (grant no. HR0011-17-2-0001).

Publisher Copyright:
© 2018 IEEE.

Publisher link

10.1109/ESSCIRC.2018.8494249

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Mousavi, N., Wang, Z., & Harjani, R. (2018). A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (pp. 246-249). Article 8494249 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2018.8494249

A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. / Mousavi, Naser; Wang, Zhiheng; Harjani, Ramesh.
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. p. 246-249 8494249 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mousavi, N, Wang, Z & Harjani, R 2018, A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference., 8494249, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 246-249, 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, 9/3/18. https://doi.org/10.1109/ESSCIRC.2018.8494249

Mousavi N, Wang Z, Harjani R. A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2018. p. 246-249. 8494249. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2018.8494249

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abstract = "An ultra-fast frequency hopping spread spectrum transceiver front-end architecture is presented that provides 20dB of processing gain at RF for the first time. This enables the receiver front-end to supress any in-band interferes by 20dB before they arrive at the LNA. The circuit consists of passive mixers and agile digital oscillator/DAC engines that are capable of quickly moving in the frequency domain with very low power. A transient hop time of 1.5ns is achieved in this design. The front-end implemented in 65nm CMOS technology, occupies an active area of 3.lmm2, and consumes 24mW (=PTX=PRX) from a 1V power supply for a center frequency of 1GHz.",

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A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection

Abstract

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