A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection

Somnath Kundu, Bongjin Kim, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations


Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase-locked loops (PLLs) [1,2]. Recent designs are trending towards an all-digital implementation that provides advantages such as compact area, good scalability and low power compared to traditional analog implementations. Achieving fractional frequency multiplication is, however, not very straightforward in MDLLs as the digitally controlled oscillator's (DCO's) edge is periodically replaced by a clean reference edge. Recently, a fractional-N MDLL was proposed in [1], where the reference edges are realigned using a digital-to-time converter (DTC). One major drawback of MDLL-based frequency synthesis is that the reference spur is generated at the output spectrum due to the timing mismatch between the phase detection path and reference injection path. One of the contributors to this timing mismatch in fully digital MDLLs is the set-up time of the D flip-flop used for phase detection that creates a static phase-offset between the DCO and reference phase under locked condition. It is very difficult to accurately cancel this offset as any digital phase-detector (PD) or time-to-digital converter (TDC) used for cancellation will have an inherent offset. A spur cancellation technique was proposed in [2] employing a gated ring oscillator (GRO)-based TDC. However, it relies on correlated-double-sampling and requires a high-resolution high-linearity TDC, which increases design complexity and power consumption. Another shortcoming of previous designs is that the timing mismatch measurement was done by looking at the spur in the output spectrum using an extensive high frequency measurement setup. This introduces off-chip measurement error and makes in-situ timing compensation schemes infeasible without a sophisticated testing setup. Furthermore, the frequency domain data must be converted to time domain, which makes it difficult to accurately estimate the exact timing mismatch. This paper proposes an all-digital fractional-N MDLL circuit where fractional-N generation is similar to the injection locking technique proposed in [3], but the advantages of subsampling techniques are utilized, hence removing the frequency divider in the feedback path. This reduces in-band phase noise and lowers power consumption. The same circuit can operate in either MDLL or PLL mode depending on the design requirement. A zero-phase-offset latch-based aperture phase-detector (APD) is designed to match the reference injection path and phase detection path precisely and thereby cancel the spur. Finally, we employ an in-situ timing detection scheme MDLL that directly measures the timing mismatch between the injected reference edge and different DCO edges, providing accurate time-domain data for MDLL characterization and tuning purposes.

Original languageEnglish (US)
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467394666
StatePublished - Feb 23 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: Jan 31 2016Feb 4 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530


Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
Country/TerritoryUnited States
CitySan Francisco


Dive into the research topics of 'A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection'. Together they form a unique fingerprint.

Cite this