A digital fractional-N subsampling multiplying delay-locked loop is proposed in this paper. A zero phase-offset latch-based aperture phase detector is introduced in a reference spur cancellation loop to precisely cancel any static phase offset (SPO) between the injected reference and the digitally controlled oscillator (DCO) phases. An in situ detection scheme is employed to directly measure this phase offset accurately by obviating the requirement of a high-speed off-chip measurement setup. Moreover, a mathematical expression is derived for the calculation of reference spur generated from a given SPO. A uniformly distributed switched capacitor-based DCO frequency tuning achieves highly linear gain. The chip prototype is fabricated in a 1.2-V supply, 65-nm LP CMOS technology and covers an output frequency range of 0.2-1.45 GHz while occupying a core area of 0.054 mm2. Measured phase noise at 1.4175 GHz is -95 dBc/Hz at 100-kHz offset, which is 9 dB lower than in phase-locked loop mode of operation.
- Aperture phase detector (APD)
- Digitally controlled oscillator (DCO)
- Multiplying delay-locked loop (MDLL)
- Phase-locked loop (PLL)
- Reference spur
- Static phase offset (SPO)