Abstract
The design of a 6-bit 50 MHz CMOS current-subtracting two-step flash A/D converter in 1.2 μm CMOS technology is described. The two-step current-subtracting technique reduces the number of current comparators and their resolution requirements thus reducing both area and power. A new design for a high speed current subtractor is presented. A differential positive feedback technique is used in the current comparators to increase speed while maintaining high resolution. The complete A/D converter, including encoding logic, operates at 50 MHz and dissipates a maximum of 25 mW.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 465-468 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 5 |
| State | Published - Dec 1 1994 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |