50 nm vertical replacement-gate (VRG) pMOSFETs

Sang Hyun Oh, J. M. Hergenrother, T. Nigam, D. Monroe, F. P. Klemens, A. Kornblit, W. M. Mansfield, M. R. Baker, D. L. Barr, F. H. Baumann, K. J. Bolan, T. Boone, N. A. Ciampa, R. A. Cirelli, D. J. Eaglesham, E. J. Ferry, A. T. Fiory, J. Frackoviak, J. P. Garno, H. J. GossmannJ. L. Grazul, M. L. Green, S. J. Hillenius, R. W. Johnson, R. C. Keller, C. A. King, R. N. Kleiman, J. T.C. Lee, J. F. Miner, M. D. Morris, C. S. Rafferty, J. M. Rosamilia, K. Short, T. W. Sorsch, A. G. Timko, G. R. Weber, G. D. Wilk, J. D. Plummer

Research output: Contribution to journalArticlepeer-review

19 Scopus citations


We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year (1), these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per μm of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with tOX = 25 Å drive 615 μA/μm at 1.5 V with IOFF = 8 nA/μm - 80% more drive than specified in the 1999 ITRS Roadmap at the same IOFF. We demonstrate 50 nm VRG-pMOSFETs with tOX = 25 Å that approach the 1.0 V roadmap target of ION = 350 μA/μm at IOFF = 20 nA/μm without the need for a hyperthin (< 20 Å) gate oxide.

Original languageEnglish (US)
Pages (from-to)65-68
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 2000


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