4x12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS

Taehyoun Oh; Ramesh Harjani

doi:10.1109/VLSIC.2012.6243829

4x12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS

Taehyoun Oh, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10 ^-8 BER, while consuming only 0.96 pJ/b/lane.

Original language	English (US)
Title of host publication	2012 Symposium on VLSI Circuits, VLSIC 2012
Pages	140-141
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243829
State	Published - Sep 28 2012
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States Duration: Jun 13 2012 → Jun 15 2012

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Other	2012 Symposium on VLSI Circuits, VLSIC 2012
Country/Territory	United States
City	Honolulu, HI
Period	6/13/12 → 6/15/12

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10.1109/VLSIC.2012.6243829

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title = "4x12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS",

abstract = "A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10 -8 BER, while consuming only 0.96 pJ/b/lane.",

author = "Taehyoun Oh and Ramesh Harjani",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/VLSIC.2012.6243829",

language = "English (US)",

isbn = "9781467308458",

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booktitle = "2012 Symposium on VLSI Circuits, VLSIC 2012",

note = "2012 Symposium on VLSI Circuits, VLSIC 2012 ; Conference date: 13-06-2012 Through 15-06-2012",

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AU - Harjani, Ramesh

PY - 2012/9/28

Y1 - 2012/9/28

N2 - A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10 -8 BER, while consuming only 0.96 pJ/b/lane.

AB - A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10 -8 BER, while consuming only 0.96 pJ/b/lane.

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U2 - 10.1109/VLSIC.2012.6243829

DO - 10.1109/VLSIC.2012.6243829

M3 - Conference contribution

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SP - 140

EP - 141

BT - 2012 Symposium on VLSI Circuits, VLSIC 2012

T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012

Y2 - 13 June 2012 through 15 June 2012

ER -

4x12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS

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