4 × 12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process

The demand for higher throughput combined with the finite number of I/Os has increased the need for higher data rates per pin [1-6]. Unfortunately, this usually results in increased inter-symbol interference and crosstalk noise, demanding larger power consumption for signal amplification and equalization. Conventionally, crosstalk has been handled by board-level techniques i.e. maintaining sufficient distance between channels or shielding signal channels. Choosing differential I/Os instead of single-ended can reduce crosstalk but at the cost of doubling the number of I/O pads and increases power consumption.