3D placement and routing

Pingqiang Zhou; Sachin S Sapatnekar

doi:10.1201/b19225

3D placement and routing

Pingqiang Zhou
, Sachin S Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

A critical part of building a successful 3D system lies in the ability to physically arrange the circuitry in such a way that manages myriad complexities related to thermal management, wire length optimization, and communication overheads. This chapter first presents an overview of methods for 3D placement, both under TSV-based and monolithic integration models. Next, it discusses algorithms for 3D routing for gate-level design after placement. Finally, methods for optimized chip-level communication using 3D NoCs are discussed.

Original language	English (US)
Title of host publication	Physical Design for 3D Integrated Circuits
Publisher	CRC Press
Pages	83-100
Number of pages	18
ISBN (Electronic)	9781498710374
ISBN (Print)	9781498710367
DOIs	https://doi.org/10.1201/b19225
State	Published - Jan 1 2017

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3D placement and routing

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