3D placement and routing

Pingqiang Zhou, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

A critical part of building a successful 3D system lies in the ability to physically arrange the circuitry in such a way that manages myriad complexities related to thermal management, wire length optimization, and communication overheads. This chapter first presents an overview of methods for 3D placement, both under TSV-based and monolithic integration models. Next, it discusses algorithms for 3D routing for gate-level design after placement. Finally, methods for optimized chip-level communication using 3D NoCs are discussed.

Original languageEnglish (US)
Title of host publicationPhysical Design for 3D Integrated Circuits
PublisherCRC Press
Pages83-100
Number of pages18
ISBN (Electronic)9781498710374
ISBN (Print)9781498710367
DOIs
StatePublished - Jan 1 2017

Fingerprint Dive into the research topics of '3D placement and routing'. Together they form a unique fingerprint.

Cite this