3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression

  • Gokul Krishnan
  • , Gopikrishnan Raveendran Nair
  • , Jonghyun Oh
  • , Anupreetham Anupreetham
  • , Pragnya Sudershan Nalla
  • , Ahmed Hassan
  • , Injune Yeo
  • , Kishore Kasichainula
  • , Jae Sun Seo
  • , Mingoo Seok
  • , Yu Cao

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Scopus citations

    Abstract

    A dynamic vision sensor (DVS) outputs a sequence of digital events, each representing a change in brightness at a particular time. As DVS keeps scaling down the pixel size and increasing the resolution, a larger volume of data is generated at limited bandwidth, resulting in reduced system-level throughput, as shown in Fig. 1(a). Hence, conventional interconnect solutions cannot meet the requirement of real-time data output from a high-speed DVS.

    Original languageEnglish (US)
    Title of host publication2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9798350330038
    DOIs
    StatePublished - 2023
    Event19th IEEE Asian Solid-State Circuits Conference, A-SSCC 2023 - Haikou, China
    Duration: Nov 5 2023Nov 8 2023

    Publication series

    Name2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023

    Conference

    Conference19th IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
    Country/TerritoryChina
    CityHaikou
    Period11/5/2311/8/23

    Bibliographical note

    Publisher Copyright:
    © 2023 IEEE.

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