3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems

Kiarash Bazargan, Ryan Kastner, Majid Sarrafzadeh

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

The advances in the programmable hardware have lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to solve before any practical general-purpose reconfigurable system is built. One fundamental problem is the placement of the modules on the reconfigurable functional unit (RFU). In reconfigurable systems, we are interested both in online placement, where the arrival time of tasks is determined at runtime and is not known a priori, and offline in which the schedule is known at compile time. In the case of offline placement, we are willing to spend more time during compile time to find a compact floorplan for the RFU modules and utilize the RFU area more efficiently. In this paper we present offline placement algorithms based on simulated annealing and greedy methods and show the superiority of their placements over the ones generated by an online algorithm.

Original languageEnglish (US)
Pages (from-to)329-338
Number of pages10
JournalDesign Automation for Embedded Systems
Volume5
Issue number3
DOIs
StatePublished - 2000
Externally publishedYes
Event10th IEEE International Workshop on Rapid System Prototyping (RSP'99) - Tampa, FL, USA
Duration: Jun 16 1999Jun 18 1999

Bibliographical note

Funding Information:
This work was supported by DARPA under contract number DABT63-97-C-0035.

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