2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

Yun Nan Chang, Hiroshi Suzuki, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

54 Scopus citations


This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r = 1/3 and the constraint length K = 9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-μm CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

Original languageEnglish (US)
Pages (from-to)826-834
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number6
StatePublished - 2000

Bibliographical note

Funding Information:
Manuscript received June 17, 1999; revised March 1, 2000. This work was supported by Defense Advanced Research Project Agency under Contract DA/DABT63-96-C-0050.


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