2. High-performance design techniques in nanometer integrated circuits

K. Roy, Sachin S Sapatnekar, R. Secareanu, Y. I. Ismail

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A key enabler of lifestyle technologies that are expected to be pervasive in the next decade will be due to the increased performance of integrated circuits. This next generation of circuits will have to overcome a significantly different set of issues from conventional technologies, and this tutorial provides the attendee with an appreciation for and an introduction to techniques used to solve these problems. The analysis and design of future generations of integrated circuits operating at frequencies in excess of 10 GHz faces major challenges that will severely impact commonly used circuit design techniques and CAD tools. A conventional definition of high-performance that places paramount importance on high speed is no longer viable, and the paradigm will change significantly in the future as other factors must be considered. Next-generation design techniques will also be impacted by trends in technology scaling that seriously impact circuit styles and CAD tools, such as lower resistivity interconnect (such as copper), low K dielectrics, faster devices (such as SOI and SiGe technologies), improved cooling techniques, and wider busses. This tutorial addresses design and CAD techniques to be used in nanometer technologies, where feature sizes will be below 100nm. Today's high-end designs are already entering this regime, with designs entering the 90nm technology node at target frequencies of 5 GHz. In such an environment, high-performance design will imply the simultaneous optimization of delay, power dissipation, signal integrity, and circuit reliability. Moreover, design will have to be carried out in an environment where process variations will see larger changes within-die and across-die than in current technologies.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5-210
Number of pages206
ISBN (Electronic)0780379918
DOIs
StatePublished - Jan 1 2003
EventTutorial Guide: 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003 - Bangkok, Thailand
Duration: May 25 2003May 28 2003

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

Other

OtherTutorial Guide: 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
CountryThailand
CityBangkok
Period5/25/035/28/03

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Roy, K., Sapatnekar, S. S., Secareanu, R., & Ismail, Y. I. (2003). 2. High-performance design techniques in nanometer integrated circuits. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 5-210). [1490897] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TUTCAS.2003.1490897