In this paper we present a novel common-mode elimination technique for a 1V rail-to-rail CMOS amplifier. For 1V single supply voltage, the input signal compression technique () is used to avoid the dead zone of input stage. Before the conventional PMOS input amplifier, the original signal is processed by the common mode elimination block which is composed with signal compression block, signal inverting block and 4 resistors. After this common mode elimination block, the original common mode signal variation from 0V to 1V is compressed with about 3.7mV variation while the compression rate of differential signal is about 71.4%. With this technique, ultra high CMRR (min 115.1dB) is obtained with 43.3dB differential gain. Cadence SPECTRE simulator and TSMC 0.25-μm CMOS technology are used to simulate this work.