100 MHz pipelined RLS adaptive filter

Kalavai J. Raghunath; Keshab K Parhi

100 MHz pipelined RLS adaptive filter

Kalavai J. Raghunath
, Keshab K Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

Recently, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2μ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter.

Original language	English (US)
Pages (from-to)	3187-3190
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	5
State	Published - 1995
Event	Proceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5) - Detroit, MI, USA Duration: May 9 1995 → May 12 1995

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@article{00c8f9ab326e46e7b2af8077aad0a9e6,

title = "100 MHz pipelined RLS adaptive filter",

abstract = "Recently, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2μ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter.",

author = "Raghunath, \{Kalavai J.\} and Parhi, \{Keshab K\}",

year = "1995",

language = "English (US)",

volume = "5",

pages = "3187--3190",

journal = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

issn = "0736-7791",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5) ; Conference date: 09-05-1995 Through 12-05-1995",

}

TY - JOUR

T1 - 100 MHz pipelined RLS adaptive filter

AU - Raghunath, Kalavai J.

AU - Parhi, Keshab K

PY - 1995

Y1 - 1995

N2 - Recently, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2μ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter.

AB - Recently, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2μ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter.

UR - https://www.scopus.com/pages/publications/0029216992

UR - https://www.scopus.com/pages/publications/0029216992#tab=citedBy

M3 - Conference article

AN - SCOPUS:0029216992

SN - 0736-7791

VL - 5

SP - 3187

EP - 3190

JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

T2 - Proceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5)

Y2 - 9 May 1995 through 12 May 1995

ER -

100 MHz pipelined RLS adaptive filter

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