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Sachin S Sapatnekar

1990 …2025

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  • 2007

    DAG based library-free technology mapping

    Marques, F. S., Rosa, L. S., Ribas, R. P., Sapatnekar, S. S. & Reis, A. I., 2007, GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI. p. 293-298 6 p. 1228857. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    27 Scopus citations

  • Module assignment for pin-limited designs under the stacked-Vdd paradigm

    Yong, Z., Tianpei, Z. & Sapatnekar, S. S., 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD. p. 656-659 4 p. 4397340. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    10 Scopus citations

  • NBTI-aware synthesis of digital circuits

    Kumar, S. V., Kim, C. H. & Sapatnekar, S. S., 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. p. 370-375 6 p. 4261208. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    166 Scopus citations

  • Placement of 3D ICs with thermal and interlayer via considerations

    Goplen, B. & Sapatnekar, S., 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. p. 626-631 6 p. 4261258. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    96 Scopus citations

  • Probabilistic congestion prediction with partial blockages

    Li, Z., Alpert, C. J., Quay, S. T., Sapatnekar, S. & Shi, W., 2007, Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007. p. 841-846 6 p. 4149138. (Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    6 Scopus citations

  • Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift

    Gu, J., Sapatnekar, S. S. & Kim, C., 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. p. 87-92 6 p. 4261149. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    13 Scopus citations
  • 2006

    A fixed-die floorplanning algorithm using an analytical approach

    Zhan, Y., Feng, Y. & Sapatnekar, S. S., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 771-776 6 p. 1594779. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    32 Scopus citations

  • An analytical model for negative bias temperature instability

    Kumar, S. V., Kim, C. H. & Sapatnekar, S. S., 2006, Proceedings of the 2006 International Conference on Computer-Aided Design, ICCAD. p. 493-496 4 p. 4110220. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    185 Scopus citations

  • Comparing simulation techniques for microarchitecture-aware floorplanning

    Nookala, V., Chen, Y., Lilja, D. J. & Sapatnekar, S. S., Nov 14 2006, ISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 2006. Vol. 2006. p. 80-88 9 p. 1620792

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    1 Scopus citations

  • Electrothermal analysis and optimization techniques for nanoscale integrated circuits

    Zhan, Y., Goplen, B. & Sapatnekar, S. S., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 219-222 4 p. 1594685. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    25 Scopus citations

  • Fast disjoint transistor networks from BDDs

    Da Rosa, L. S., Marques, F. S., Cardoso, T. M. G., Ribas, R. P., Sapatnekar, S. S. & Reis, A. I., Nov 16 2006, Proceedings SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design. p. 137-142 6 p. (SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    13 Scopus citations

  • Impact of NBTI on SRAM read stability and design for reliability

    Kumar, S. V., Kim, C. H. & Sapatnekar, S. S., 2006, Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006. p. 210-218 9 p. 1613138. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    258 Scopus citations

  • Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

    Kumar, S. V., Kim, C. H. & Sapatnekar, S. S., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 559-564 6 p. 1594744. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    19 Scopus citations

  • Physical design automation challenges for 3D ICs

    Sapatnekar, S. S., 2006, 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. IEEE Computer Society, 1669407. (2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    6 Scopus citations

  • Statistical timing analysis with correlated non-gaussian parameters using independent component analysis

    Singh, J. & Sapatnekar, S. S., 2006, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., p. 155-160 6 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    89 Scopus citations

  • Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing

    Keane, J., Eom, H., Kim, T. H., Sapatnekar, S. S. & Kim, C. H., 2006, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., p. 425-428 4 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    60 Scopus citations

  • Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis

    Nookala, V., Lilja, D. J. & Sapatnekar, S. S., 2006, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. p. 298-303 6 p. (Proceedings of the International Symposium on Low Power Electronics and Design; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    24 Scopus citations

  • Temperature-aware routing in 3D ICs

    Zhang, T., Zhan, Y. & Sapatnekar, S. S., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 309-314 6 p. 1594700. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Open Access
    91 Scopus citations

  • Width quantization aware FinFET circuit design

    Gu, J., Keane, J., Sapatnekar, S. S. & Kim, C. H., Dec 1 2006, Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006. p. 337-340 4 p. 4114973. (Proceedings of the Custom Integrated Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    32 Scopus citations
  • 2005

    A high efficiency full-chip thermal simulation algorithm

    Zhan, Y. & Sapatnekar, S. S., 2005, Proceedings of theICCAD-2005: International Conference on Computer-Aided Design. Institute of Electrical and Electronics Engineers Inc., p. 635-638 4 p. 1560144. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    53 Scopus citations

  • A hybrid linear equation solver and its application in quadratic placement

    Qian, H. & Sapatnekar, S. S., 2005, Proceedings of theICCAD-2005: International Conference on Computer-Aided Design. Institute of Electrical and Electronics Engineers Inc., p. 905-909 5 p. 1560190. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    23 Scopus citations

  • Buffering global interconnects in structured ASIC design

    Zhang, T. & Sapatnekar, S. S., 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. p. 23-26 4 p. 1466123. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    5 Scopus citations

  • Exact lower bound for the number of switches in series to implement a combinational logic cell

    Schneider, F. R., Ribas, R. P., Sapatnekar, S. S. & Reis, A. I., 2005, Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. p. 357-362 6 p. 1524175. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    15 Scopus citations

  • Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up

    Zhan, Y. & Sapatnekar, S. S., Dec 1 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. p. 87-92 6 p. 1466136. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    48 Scopus citations

  • Thermal via placement in 3D ICs

    Goplen, B. & Sapatnekar, S., Dec 27 2005, Proceedings of ISPD'05 - 2005 International Symposium on Physical Design. p. 167-174 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    156 Scopus citations
  • 2004

    Accurate estimation of global buffer delay within a floorplan

    Alpert, C. J., Hu, J., Sapatnekar, S. S. & Sze, C. N., 2004, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 706-711 6 p. 9A.3. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    21 Scopus citations

  • A chip-level electrostatic discharge simulation strategy

    Qian, H., Kozhaya, J. N., Nassif, S. R. & Sapatnekar, S. S., Dec 1 2004, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 315-318 4 p. 4D.1. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    11 Scopus citations

  • Fast comparisons of circuit implementations

    Karandikar, S. K. & Sapatnekar, S. S., 2004, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Gielen, G. & Figueras, J. (eds.). p. 910-915 6 p. (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; vol. 2).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    7 Scopus citations

  • Logical effort based technology mapping

    Karandikar, S. K. & Sapatnekar, S. S., 2004, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 419-422 4 p. 5D.2. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    13 Scopus citations

  • Optimization of integrated spiral inductors using sequential quadratic programming

    Yong, Z. & Sapatnekar, S. S., 2004, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2004. p. 622-629 8 p. 1268914. (Proceedings -Design, Automation and Test in Europe, DATE; vol. 1).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    7 Scopus citations

  • Optimization of integrated spiral inductors using sequential quadratic programming

    Zhan, Y. & Sapatnekar, S. S., 2004, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Gielen, G. & Figueras, J. (eds.). p. 622-627 6 p. (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; vol. 1).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    20 Scopus citations

  • Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

    Zhang, T. & Sapatnekar, S. S., 2004, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. p. 93-98 6 p. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    8 Scopus citations

  • Transistor and pin reordering for gate oxide leakage reduction in dual T ox circuits

    Sultania, A. K., Sylvester, D. & Sapatnekar, S. S., 2004, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. p. 228-233 6 p. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    14 Scopus citations
  • 2003

    2. High-performance design techniques in nanometer integrated circuits

    Roy, K., Sapatnekar, S. S., Secareanu, R. & Ismail, Y. I., Jan 1 2003, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 5-210 206 p. 1490897. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 1).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

    Goplen, B. & Sapatnekar, S., 2003, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 86-89 4 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    236 Scopus citations

  • Partition-driven standard cell thermal placement

    Chen, G. & Sapatnekar, S., Jul 28 2003, Proceedings of the International Symposium on Physical Design. p. 75-80 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    56 Scopus citations
  • 2002

    An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

    Su, H., Sapatnekar, S. S. & Nassif, S. R., Jan 1 2002, Proceedings of the International Symposium on Physical Design. p. 68-73 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    62 Scopus citations

  • An efficient algorithm for low power pass transistor logic synthesis

    Shelar, R. S. & Sapatnekar, S. S., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 87-92 6 p. 994890. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    16 Scopus citations

  • Proceedings of the International Symposium on Physical Design: Foreword

    Pedram, M. & Sapatnekar, S., Jan 1 2002, Proceedings of the International Symposium on Physical Design.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • 2001

    Buffered Steiner trees for difficult instances

    Alpert, C. J., Hrkic, M., Hu, J., Kahng, A. B., Lillis, J., Liu, B., Quay, S. T., Sapatnekar, S. S., Sullivan, A. J. & Villarrubia, P., Jan 1 2001, Proceedings of the International Symposium on Physical Design. p. 4-9 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    28 Scopus citations

  • Proceedings of the International Symposium on Physical Design: Foreword

    Sapatnekar, S. & Wiesel, M., Jan 1 2001, Proceedings of the International Symposium on Physical Design.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Steiner tree optimization for buffers. Blockages and bays

    Alpert, C. J., Gandham, G., Hu, J., Neves, J. L., Quay, S. T. & Sapatnekar, S. S., Jan 1 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 399-402 4 p. 922069. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    7 Scopus citations

  • Steiner tree optimization for buffers. Blockages and bays

    Alpert, C. J., Gandham, G., Hu, J., Neves, J. L., Quay, S. T. & Sapatnekar, S. S., Jan 1 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 399-402 4 p. 922069. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Tutorial: Optimization and analysis techniques for the deep submicron regime

    Menezes, N. & Sapatnekar, S., Jan 1 2001, Proceedings of the IEEE International Conference on VLSI Design. p. 3-4 2 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • 2000

    A timing-constrained algorithm for simultaneous global routing of multiple nets

    Hu, J. & Sapatnekar, S. S., 2000, IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000. Institute of Electrical and Electronics Engineers Inc., p. 99-103 5 p. 896457. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2000-January).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    52 Scopus citations

  • Capturing the effect of crosstalk on delay

    Sapatnekar, S. S., Jan 1 2000, Proceedings of the IEEE International Conference on VLSI Design. IEEE, p. 364-369 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    15 Scopus citations

  • Fast analysis and optimization of power/ground networks

    Su, H., Gala, K. H. & Sapatnekar, S. S., 2000, IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000. Institute of Electrical and Electronics Engineers Inc., p. 477-480 4 p. 896518. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2000-January).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    80 Scopus citations
  • 1998

    Fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

    Jiang, Y., Sapatnekar, S. S. & Bamji, C., Dec 1 1998, VLSI in Computers and Processors. IEEE, p. 276-281 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    1 Scopus citations

  • Routing tree topology construction to meet interconnect timing constraints

    Hou, H. & Sapatnekar, S. S., Jan 1 1998, Proceedings of the International Symposium on Physical Design. Anon (ed.). ACM, p. 205-210 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    6 Scopus citations
  • 1997

    Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs

    Kim, J., Bamji, C., Jiang, Y. & Sapatnekar, S., Jan 1 1997, Proceedings of the International Symposium on Physical Design. p. 130-135 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    8 Scopus citations