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Sachin S Sapatnekar

1990 …2022

Research output per year

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Projects

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VeriGOOD-ML: Verilog Generator (Open-source), Optimized for Designs for Machine Learning

Sapatnekar, S. S.

USDOD DEFENSE ADV RES PROJECTS

12/30/19 → 6/29/21

Project: Research project

ALIGN: Analog Layout, Intelligently Generated from Netlists

Sapatnekar, S. S. & Harjani, R.

SPAWAR

8/13/18 → 8/12/20

Project: Research project

OpenROAD: Foundations and Realization of Open, Accessibl

Sapatnekar, S. S.

University of California San Diego

6/1/18 → 7/21/20

Project: Research project

SHF: Medium: Time Based Deep Neural Networks: An Integra

Kim, C. H., Sapatnekar, S. S. & Zhao, Q.

National Science Foundation

5/1/18 → 4/30/22

Project: Research project

SHF:Small:Enchancing the Reliability of Mixed-Signal Int

Sapatnekar, S. S.

National Science Foundation

9/1/17 → 8/31/20

Project: Research project

Mitigating Reliability Issues in Analog Circuits

Kim, C. H. & Sapatnekar, S. S.

University of Texas at Dallas

3/1/17 → 5/31/20

Project: Research project