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Sachin S Sapatnekar

1990 …2022
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Fingerprint The Fingerprint is created by mining the titles and abstracts of the person's research outputs and projects/funding awards to create an index of weighted terms from discipline-specific thesauri.

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Projects 1998 2022

ALIGN: Analog Layout, Intelligently Generated from Netlists

Sapatnekar, S. S. & Harjani, R.

SPAWAR

8/13/18 → 8/12/19

Project: Research project

OpenROAD: Foundations and Realization of Open, Accessibl

Sapatnekar, S. S.

University of California San Diego

6/1/18 → 5/31/19

Project: Research project

SHF: Medium: Time Based Deep Neural Networks: An Integra

Kim, C. H., Sapatnekar, S. S. & Zhao, Q.

National Science Foundation

5/1/18 → 4/30/22

Project: Research project

Software

SHF:Small:Enchancing the Reliability of Mixed-Signal Int

Sapatnekar, S. S.

National Science Foundation

9/1/17 → 8/31/20

Project: Research project

SHF: Small: Collaborative Research: Variation-Resilient

Sapatnekar, S. S.

National Science Foundation

8/1/15 → 7/31/19

Project: Research project

Research

Research Output 1990 2019

An analytical approach for error PMF characterization in approximate circuits

Sengupta, D., Snigdha, F. S., Hu, J. & Sapatnekar, S. S., Jan 1 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 1, p. 70-83 14 p., 8283743.

Research output: Contribution to journal › Article

Networks (circuits)
Hardware
Adders
Error analysis
Probability distributions

Dynamic Approximation of JPEG Hardware

Snigdha, F. S., Sengupta, D., Hu, J. & Sapatnekar, S. S., Feb 1 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 295-308 14 p., 8299430.

Research output: Contribution to journal › Article

Hardware
Discrete cosine transforms
Pixels

SEFACT: Selective feature activation and early classification for CNNs

Snigdha, F. S., Ahmed, I., Manasi, S. D., Mankalale, M. G., Hu, J. & Sapatnekar, S. S., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 526-531 6 p.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

A simple yet efficient accuracy-configurable adder design

Xu, W., Sapatnekar, S. S. & Hu, J., Jun 1 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 6, p. 1112-1125 14 p.

Research output: Contribution to journal › Article

Adders
Error detection
Discrete cosine transforms
Error correction
Redundancy

Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs

Marella, S. K. & Sapatnekar, S. S., Dec 1 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 12, p. 2907-2920 14 p., 8463602.

Research output: Contribution to journal › Article

Networks (circuits)
Transistors
Silicon
Threshold voltage
Integrated circuits

Datasets

Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm

Hu, J. (Creator), Sapatnekar, S. S. (Creator), Sengupta, D. (Creator), Snigdha, F. (Creator), Data Repository for the University of Minnesota, 2017

DOI: 10.13020/D6BP4X, https://doi.org/10.13020/D6BP4X

Dataset