Projects per year
Fingerprint The Fingerprint is created by mining the titles and abstracts of the person's research outputs and projects/funding awards to create an index of weighted terms from discipline-specific thesauri.
- 9 Similar Profiles
Networks (circuits)
Engineering & Materials Science
Transistors
Engineering & Materials Science
Wire
Engineering & Materials Science
Electromigration
Engineering & Materials Science
Clocks
Engineering & Materials Science
Integrated circuits
Engineering & Materials Science
Digital circuits
Engineering & Materials Science
Delay circuits
Engineering & Materials Science
Network
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Projects 1998 2022
ALIGN: Analog Layout, Intelligently Generated from Netlists
Sapatnekar, S. S. & Harjani, R.
8/13/18 → 8/12/20
Project: Research project
OpenROAD: Foundations and Realization of Open, Accessibl
University of California San Diego
6/1/18 → 7/21/20
Project: Research project
SHF: Medium: Time Based Deep Neural Networks: An Integra
Sapatnekar, S. S., Zhao, Q. & Kim, C. H.
5/1/18 → 4/30/22
Project: Research project
Software
Mitigating Reliability Issues in Analog Circuits
Sapatnekar, S. S. & Kim, C. H.
3/1/17 → 12/31/19
Project: Research project
Analog circuits
Research Output 1990 2019
2.5 A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control
Everson, L. R., Sapatnekar, S. S. & Kim, C. H., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 50-52 3 p. 8662455. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Wavefronts
Application specific integrated circuits
Data storage equipment
Pulse shaping
Computer architecture
An analytical approach for error PMF characterization in approximate circuits
Sengupta, D., Snigdha, F. S., Hu, J. & Sapatnekar, S. S., Jan 1 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 1, p. 70-83 14 p., 8283743.Research output: Contribution to journal › Article
Networks (circuits)
Hardware
Adders
Error analysis
Probability distributions
An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology
Perricone, R., Liang, Z., Mankalale, M. G., Niemier, M., Sapatnekar, S. S., Wang, J. & Hu, X. S., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 390-395 6 p. 8714916. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Flip flop circuits
Flip
Energy Efficient
Spintronics
Composite
Dynamic Approximation of JPEG Hardware
Snigdha, F. S., Sengupta, D., Hu, J. & Sapatnekar, S. S., Feb 1 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 295-308 14 p., 8299430.Research output: Contribution to journal › Article
Hardware
Discrete cosine transforms
Pixels
Electromigration-aware interconnect design
Sapatnekar, S. S., Apr 4 2019, ISPD 2019 - Proceedings of the 2019 International Symposium on Physical Design. Association for Computing Machinery, p. 83-90 8 p. (Proceedings of the International Symposium on Physical Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Electromigration
Wire
Digital circuits
Clocks
Servers
Datasets
Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm
Hu, J., Sapatnekar, S. S., Sengupta, D., Sharmin Snigdha, F., Data Repository for the University of Minnesota, 2017
DOI: 10.13020/D6BP4X, https://doi.org/10.13020/D6BP4X
Dataset