Projects per year
Fingerprint The Fingerprint is created by mining the titles and abstracts of the person's research outputs and projects/funding awards to create an index of weighted terms from discipline-specific thesauri.
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Projects
VeriGOOD-ML: Verilog Generator (Open-source), Optimized for Designs for Machine Learning
USDOD DEFENSE ADV RES PROJECTS
12/30/19 → 6/29/21
Project: Research project
ALIGN: Analog Layout, Intelligently Generated from Netlists
Sapatnekar, S. S. & Harjani, R.
8/13/18 → 8/12/21
Project: Research project
OpenROAD: Foundations and Realization of Open, Accessibl
University of California San Diego
6/1/18 → 7/21/20
Project: Research project
SHF: Medium: Time Based Deep Neural Networks: An Integra
Kim, C. H., Sapatnekar, S. S. & Zhao, Q.
5/1/18 → 4/30/22
Project: Research project
Research Output
Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage
Fan, Q., Lilja, D. J. & Sapatnekar, S. S., Feb 1 2020, In : IEEE Transactions on Computers. 69, 2, p. 239-252 14 p., 8865439.Research output: Contribution to journal › Article
A DNA Read Alignment Accelerator Based on Computational RAM
Chowdhury, Z. I., Zabihi, M., Khatamifard, S. K., Zhao, Z., Resch, S., Razaviyayn, M., Wang, J. P., Sapatnekar, S. S. & Karpuzcu, U. R., Jun 2020, In : IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 6, 1, p. 80-88 9 p., 9064820.Research output: Contribution to journal › Article
Open Access
A Shortest Path Finding Time-Based Accelerator Core with Built-in Gravity Control and Buffer Zone for Smooth 3-D Navigation
Everson, L. R., Song, J., Sapatnekar, S. S. & Kim, C. H., 2020, In : IEEE Solid-State Circuits Letters. 3, p. 66-69 4 p., 9097891.Research output: Contribution to journal › Article
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
Kunal, K., Dhar, T., Madhusudan, M., Poojary, J., Sharma, A., Xu, W., Burns, S. M., Hu, J., Harjani, R. & Sapatnekar, S. S., Mar 2020, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 55-60 6 p. 9116329. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Learning from experience: Applying ML to analog circuit design
Kunal, K., Dhar, T., Li, Y., Madhusudan, M., Poojary, J., Sharma, A. K., Xu, W., Burns, S. M., Harjani, R., Hu, J., Mukherjee, P. & Sapatnekar, S. S., Sep 20 2020, ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, 1 p. (Proceedings of the International Symposium on Physical Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Open Access
Datasets
Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm
Hu, J., Sapatnekar, S. S., Sengupta, D. & Sharmin Snigdha, F., Data Repository for the University of Minnesota, 2017
DOI: 10.13020/D6BP4X, https://doi.org/10.13020/D6BP4X
Dataset