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Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Collaborations and top research areas from the last five years
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Projects
- 22 Finished
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Passive Tile Architecture for MAX
Harjani, R. (PI) & Parhi, K. K. (CoI)
BAE SYSTEMS LAND & ARMAMENTS HOLDINGS, USDOD DEFENSE ADV RES PROJECTS
4/24/23 → 8/21/24
Project: Research project
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ALIGN Analog Layout Design Suite
Harjani, R. (PI)
THE NATIONAL SCIENCE FOUNDATION
3/1/23 → 2/29/24
Project: Research project
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Automated Layout Of Analog Arrays In Advanced Technology Nodes
Sapatnekar, S. S. (PI) & Harjani, R. (CoI)
UNIVERSITY OF TEXAS AT DALLAS, SEMICONDUCTOR RESEARCH CORPORATION
1/1/22 → 12/31/24
Project: Research project
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ALIGN: Analog Layout, Intelligently Generated from Netlists
Sapatnekar, S. S. (PI) & Harjani, R. (CoI)
8/13/18 → 2/12/23
Project: Research project
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Direct Battery-to-Silicon Power Transfer in Advanced Nan
Harjani, R. (PI)
3/1/17 → 5/31/20
Project: Research project
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A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process
Cho, K. U., Gil, J., Park, C., Cho, K. J., Shin, J. W., Kim, E. S., Eo, Y. S., Harjani, R., Kim, N. Y. & Oh, T., 2024, In: IEEE Access. 12, p. 142677-142694 18 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
An Efficient Real-Valued Cross-Correlator via Fast Fourier Transform
Chiu, S. W., Harjani, R. & Parhi, K. K., 2024, Proceedings - 2024 IEEE Workshop on Signal Processing Systems, SiPS 2024. Institute of Electrical and Electronics Engineers Inc., p. 195-200 6 p. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Automated synthesis of mixed-signal ML inference hardware under accuracy constraints
Kunal, K., Poojary, J., Ramprasath, S., Harjani, R. & Sapatnekar, S. S., 2024, ASP-DAC 2024 - 29th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 478-483 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits under Nonlinear Gradients
Sharma, A. K., Madhusudan, M., Burns, S. M., Yaldiz, S., Mukherjee, P., Harjani, R. & Sapatnekar, S. S., 2024, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43, 12, p. 4373-4385 13 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs
Karmokar, N., Harjani, R. & Sapatnekar, S. S., 2024, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review