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Research Output 1986 2019

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Article
1996
1 Citation (Scopus)

Star RLS lattice adaptive filters

Li, Y. & Parhi, K. K., Jan 1 1996, In : Proceedings - IEEE International Symposium on Circuits and Systems. 2, p. 389-392 4 p.

Research output: Contribution to journalArticle

Adaptive filters
Stars
Adaptive filtering
Computer simulation

Synthesis of low area data format converters

Majumdar, M. & Parhi, K. K., Jan 1 1996, In : Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. 145-148 4 p.

Research output: Contribution to journalArticle

Processing
5 Citations (Scopus)

Two-dimensional retiming with low memory requirements

Denk, T. C., Majumdar, M. & Parhi, K. K., Jan 1 1996, In : ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 6, p. 3330-3333 4 p.

Research output: Contribution to journalArticle

Throughput
Data storage equipment
requirements
Data flow graphs
Memory architecture
4 Citations (Scopus)

Unified framework for characterizing retiming and scheduling solutions

Denk, T. C. & Parhi, K. K., Jan 1 1996, In : Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. 568-571 4 p.

Research output: Contribution to journalArticle

Scheduling
Data flow graphs
Application specific integrated circuits
Networks (circuits)
1995
8 Citations (Scopus)

100 MHz pipelined RLS adaptive filter

Raghunath, K. J. & Parhi, K. K., Jan 1 1995, In : ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 5, p. 3187-3190 4 p.

Research output: Contribution to journalArticle

Adaptive filters
Numbering systems
Application specific integrated circuits
26 Citations (Scopus)

A Fast Radix-4 Division Algorithm and its Architecture

Srinivas, H. R. & Parhi, K. K., Jan 1 1995, In : IEEE Transactions on Computers. 44, 6, p. 826-831 6 p.

Research output: Contribution to journalArticle

Digit
Division
Remainder
Quotient
Partial
28 Citations (Scopus)

Determining the minimum iteration period of an algorithm

Ito, K. & Parhi, K. K., Dec 1 1995, In : Journal of VLSI Signal Processing. 11, 3, p. 229-244 16 p.

Research output: Contribution to journalArticle

Data flow graphs
Flow Graphs
Data Flow
Iteration
Redundancy

Generalized multiplication free arithmetic codes

Fu, B. & Parhi, K. K., Jan 1 1995, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 437-440 4 p.

Research output: Contribution to journalArticle

Image coding
41 Citations (Scopus)

High-level algorithm and architecture transformations for DSP synthesis

Parhi, K. K., Jan 1 1995, In : Journal of VLSI Signal Processing. 9, 1-2, p. 121-143 23 p.

Research output: Contribution to journalArticle

Synthesis
Look-ahead
Digital signal processing
Distributivity
Pipelining
52 Citations (Scopus)
Digital signal processing
Scheduling
Data flow graphs
Resource allocation
11 Citations (Scopus)
Hardware
13 Citations (Scopus)

Low-power FIR digital filter architectures

Pearson, D. N. & Parhi, K. K., Jan 1 1995, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 231-234 4 p.

Research output: Contribution to journalArticle

FIR filters
Digital filters
Hardware
Electric power utilization
Processing
23 Citations (Scopus)

Pipelined Adaptive DFE Architectures Using Relaxed Look-Ahead

Shanbhag, N. R. & Parhi, K. K., Jan 1 1995, In : IEEE Transactions on Signal Processing. 43, 6, p. 1368-1385 18 p.

Research output: Contribution to journalArticle

Decision feedback equalizers
Magnetic recording
Feedback
Hardware
Processing
8 Citations (Scopus)

Pipelined Lattice WDF Design for Wideband Filters

Chung, J. G., Kim, H. & Parhi, K. K., Jan 1 1995, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 42, 9, p. 616-618 3 p.

Research output: Contribution to journalArticle

Wave filters
Digital filters
Electrocardiography
Signal processing
Hardware
13 Citations (Scopus)

Resource-constrained loop list scheduler for DSP algorithms

Wang, C. Y. & Parhi, K. K., Oct 1 1995, In : Journal of VLSI Signal Processing. 11, 1-2, p. 75-96 22 p.

Research output: Contribution to journalArticle

Digital signal processing
Scheduler
Signal Processing
Scheduling
Iteration
6 Citations (Scopus)

Scaled Normalized Lattice Digital Filter Structures

Chung, J. G. & Parhi, K. K., Jan 1 1995, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 42, 4, p. 278-282 5 p.

Research output: Contribution to journalArticle

Digital filters
2 Citations (Scopus)

Synthesis and pipelining of ladder wave digital filters in digital domain

Chung, J. G. & Parhi, K. K., Jan 1 1995, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 77-80 4 p.

Research output: Contribution to journalArticle

Ladders
Digital filters
Microwave filters
Wave filters
Hardware
8 Citations (Scopus)

Two VLSI design advances in arithmetic coding

Fu, B. & Parhi, K. K., Jan 1 1995, In : Proceedings - IEEE International Symposium on Circuits and Systems. 2, p. 1440-1443 4 p.

Research output: Contribution to journalArticle

Image coding
Clocks
Entropy
Hardware
Degradation
1994
1 Citation (Scopus)

A C-Testable Carry-Free Divider

Srinivas, H. R., Vinnakota, B. & Parhi, K. K., Jan 1 1994, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2, 4, p. 472-488 17 p.

Research output: Contribution to journalArticle

Adders
Testing
Hardware
9 Citations (Scopus)
Discrete wavelet transforms
Digital filters
Adders
FIR filters
Processing
20 Citations (Scopus)
Discrete wavelet transforms
FIR filters
Electric delay lines
Processing
21 Citations (Scopus)
Digital signal processing
Networks (circuits)
8 Citations (Scopus)

Fast radix 4 division algorithm

Srinivas, H. R. & Parhi, K. K., Dec 1 1994, In : Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. 311-314 4 p.

Research output: Contribution to journalArticle

Costs
1 Citation (Scopus)

Finite-Precision Analysis of the Pipelined ADPCM Coder

Shanbhag, N. R. & Parhi, K. K., Jan 1 1994, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 41, 5, p. 364-368 5 p.

Research output: Contribution to journalArticle

Differential pulse code modulation
Error analysis
14 Citations (Scopus)

Input compression and efficient VLSI architectures for rank order and stack filters

Adams, G. B., Coyle, E. J., Lin, L., Lucke, L. E. & Parhi, K. K., Jan 1 1994, In : Signal Processing. 38, 3, p. 441-453 13 p.

Research output: Contribution to journalArticle

Statistics
Sorting
Decomposition
8 Citations (Scopus)

Module selection and data format conversion for cost-optimal DSP synthesis

Ito, K., Lucke, L. E. & Parhi, K. K., Dec 1 1994, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. p. 322-329 8 p.

Research output: Contribution to journalArticle

Data flow graphs
Costs
Linear programming
37 Citations (Scopus)

Parallel Processing Architectures for Rank Order and Stack Filters

Lucke, L. E. & Parhi, K. K., Jan 1 1994, In : IEEE Transactions on Signal Processing. 42, 5, p. 1178-1189 12 p.

Research output: Contribution to journalArticle

Processing
Electric power utilization
Throughput
Electric potential
19 Citations (Scopus)

Pipelining of Lattice IIR Digital Filters

Chung, J. G. & Parhi, K. K., Jan 1 1994, In : IEEE Transactions on Signal Processing. 42, 4, p. 751-761 11 p.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Transfer functions
Adaptive filtering
Poles
4 Citations (Scopus)

Sequential and Parallel Neural Network Vector Quantizers

Parhi, K. K., Wu, F. H. & Genesan, K., Jan 1 1994, In : IEEE Transactions on Computers. 43, 1, p. 104-109 6 p.

Research output: Contribution to journalArticle

Neural Networks
Neural networks
Codebook
Updating
Learning algorithms
1993
2 Citations (Scopus)
Speech coding
Degradation
Integrated circuits
Signal to noise ratio
Hardware
16 Citations (Scopus)

A Pipelined Adaptive Lattice Filter Architecture

Shanbhag, N. R. & Parhi, K. K., Jan 1 1993, In : IEEE Transactions on Signal Processing. 41, 5, p. 1925-1939 15 p.

Research output: Contribution to journalArticle

Differential pulse code modulation
Adaptive filters
Image compression
Pipelines
Hardware
20 Citations (Scopus)
Data flow graphs
Scheduling
Digital signal processing
Resource allocation
17 Citations (Scopus)

Parallel Adaptive Decision Feedback Equalizers

Raghunath, K. J. & Parhi, K. K., Jan 1 1993, In : IEEE Transactions on Signal Processing. 41, 5, p. 1956-1961 6 p.

Research output: Contribution to journalArticle

Decision feedback equalizers
Computational complexity
Hardware
36 Citations (Scopus)
Differential pulse code modulation
Adaptive filters
Signal to noise ratio
Hardware
Adaptive filtering
242 Citations (Scopus)

VLSI Architectures for Discrete Wavelet Transforms

Parhi, K. K. & Nishitani, T., Jan 1 1993, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1, 2, p. 191-202 12 p.

Research output: Contribution to journalArticle

Discrete wavelet transforms
Hardware
High pass filters
Networks (circuits)
1992
41 Citations (Scopus)

A Fast VLSI Adder Architecture

Srinivas, H. R. & Parhi, K. K., Jan 1 1992, In : IEEE Journal of Solid-State Circuits. 27, 5, p. 761-767 7 p.

Research output: Contribution to journalArticle

Adders
17 Citations (Scopus)

An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip

Hatamian, M. & Parhi, K. K., Jan 1 1992, In : IEEE Journal of Solid-State Circuits. 27, 2, p. 175-183 9 p.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Clocks
FIR filters
Networks (circuits)
2 Citations (Scopus)

Concurrent architectures for two-dimensional recursive digital filtering

Parhi, K. K. & Messerschmitt, D. G., Jan 1 1992, In : IEEE Transactions on Circuits and Systems. v, n, p. 813-829 17 p.

Research output: Contribution to journalArticle

Digital filters
Hardware
24 Citations (Scopus)
Hardware
Parallel architectures
Communication systems
Decomposition
17 Citations (Scopus)

High-speed VLSI arithmetic processor architectures using hybrid number representation

Srinivas, H. R. & Parhi, K. K., May 1 1992, In : Journal of VLSI Signal Processing. 4, 2-3, p. 177-198 22 p.

Research output: Contribution to journalArticle

High Speed
Square root
Binary
Complement
Multiplier
109 Citations (Scopus)

Synthesis of Control Circuits in Folded Pipelined DSP Architectures

Parhi, K. K., Wang, C. Y. & Brown, A. P., Jan 1 1992, In : IEEE Journal of Solid-State Circuits. 27, 1, p. 29-43 15 p.

Research output: Contribution to journalArticle

Data flow graphs
Networks (circuits)
Hardware
Resource allocation
Clocks
51 Citations (Scopus)
Digital signal processing
Networks (circuits)
8 Citations (Scopus)

Video Data Format Converters Using Minimum Number of Registers

Parhi, K. K., Jan 1 1992, In : IEEE Transactions on Circuits and Systems for Video Technology. 2, 2, p. 255-267 13 p.

Research output: Contribution to journalArticle

Pixels
1991
110 Citations (Scopus)

A systematic approach for design of digit-serial signal processing architectures

Parhi, K. K., Apr 1 1991, In : IEEE Transactions on Circuits and Systems. 38, 4, p. 358-375 18 p.

Research output: Contribution to journalArticle

Signal processing
Clocks
Parallel architectures
Adders
Hardware
13 Citations (Scopus)

Finite Word Effects in Pipelined Recursive Filters

Parhi, K. K., Jan 1 1991, In : IEEE Transactions on Signal Processing. 39, 6, p. 1450-1454 5 p.

Research output: Contribution to journalArticle

Poles
53 Citations (Scopus)

Pipelining in Algorithms with Quantizer Loops

Parhi, K. K., Jan 1 1991, In : IEEE Transactions on Circuits and Systems. 38, 7, p. 745-754 10 p.

Research output: Contribution to journalArticle

Differential pulse code modulation
Pipelines
Feedback
Decision feedback equalizers
Equalizers
15 Citations (Scopus)

Pipelining in Dynamic Programming Architectures

Parhi, K. K., Jan 1 1991, In : IEEE Transactions on Signal Processing. 39, 6, p. 1442-1450 9 p.

Research output: Contribution to journalArticle

Dynamic programming
Hardware
Parallel processing systems
Clocks
3 Citations (Scopus)

Register minimization in DSP data format converters

Parhi, K. K., Dec 1 1991, In : Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. 2367-2370 4 p.

Research output: Contribution to journalArticle

Digital signal processing
191 Citations (Scopus)

Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding

Parhi, K. K. & Messerschmitt, D. G., Jan 1 1991, In : IEEE Transactions on Computers. 40, 2, p. 178-195 18 p.

Research output: Contribution to journalArticle

Optimal Scheduling
Unfolding
Data Flow
Signal processing
Scheduling