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Research Output 1986 2019

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Article
2002
52 Citations (Scopus)

Evaluation of CORDIC algorithms for FPGA design

Valls, J., Kuhlmann, M. & Parhi, K. K., Jan 1 2002, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 32, 3, p. 207-222 16 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
FPGA Implementation
Evaluation
Operator
52 Citations (Scopus)

Fast and exact transistor sizing based on iterative relaxation

Sundararajan, V., Sapatnekar, S. S. & Parhi, K. K., May 1 2002, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21, 5, p. 568-581 14 p.

Research output: Contribution to journalArticle

Transistors
Networks (circuits)
Combinatorial circuits
Costs
Wire
38 Citations (Scopus)

Frequency spectrum based low-area low-power parallel FIR filter design

Chung, J. G. & Parhi, K. K., Sep 1 2002, In : Eurasip Journal on Applied Signal Processing. 2002, 9, p. 944-953 10 p.

Research output: Contribution to journalArticle

FIR filters
Hardware
Adders
Digital filters
Costs
10 Citations (Scopus)

High-speed add-compare-select units using locally self-resetting CMOS

Jung, G., Kong, J. J., Sobelman, G. E. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 889-892 4 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
9 Citations (Scopus)

High speed VLSI architecture design for block turbo decoder

Chi, Z. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 901-904 4 p.

Research output: Contribution to journalArticle

Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
81 Citations (Scopus)

Implementation approaches for the advanced encryption standard algorithm

Xinmiao, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Circuits and Systems Magazine. 2, 4, p. 24-46 23 p.

Research output: Contribution to journalArticle

Cryptography
Computer hardware
Feedback
Processing
5 Citations (Scopus)
Decoding
Iterative decoding
Signal to noise ratio
Hardware
Degradation
30 Citations (Scopus)

P-CORDIC: A precomputation based rotation CORDIC algorithm

Kuhlmann, M. & Parhi, K. K., Sep 1 2002, In : Eurasip Journal on Applied Signal Processing. 2002, 9, p. 936-943 8 p.

Research output: Contribution to journalArticle

Digital computers
Computer architecture
Degrees of freedom (mechanics)
Pipelines
4 Citations (Scopus)

Performance-scalable array architectures for modular multiplication

Freking, W. L. & Parhi, K. K., Jun 1 2002, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 31, 2, p. 101-116 16 p.

Research output: Contribution to journalArticle

Modular multiplication
Hardware
Systolic arrays
Cryptography
Clocks
2 Citations (Scopus)

Viterbi decoder architecture for interleaved convolutional code

Kong, J. J. & Parhi, K. K., Dec 1 2002, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 2, p. 1934-1937 4 p.

Research output: Contribution to journalArticle

Convolutional codes
Data storage equipment
Decoding
Parallel architectures
Clocks
2001
15 Citations (Scopus)

Approaches to low-power implementations of DSP systems

Parhi, K. K., Oct 1 2001, In : IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 48, 10, p. 1214-1224 11 p.

Research output: Contribution to journalArticle

Electric power utilization
FIR filters
Equalizers
Fast Fourier transforms
Digital subscriber lines

A study on the performance, complexity tradeoffs of block turbo decoder design

Chi, Z., Song, L. & Parhi, K. K., Jan 1 2001, In : Materials Research Society Symposium - Proceedings. 626

Research output: Contribution to journalArticle

decoders
tradeoffs
Decoding
decoding
very large scale integration
2 Citations (Scopus)

A unified adder design

Wang, Y. & Parhi, K. K., Jan 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 177-182 6 p.

Research output: Contribution to journalArticle

Adders
Carry logic
Transistors
11 Citations (Scopus)

A unified algebraic transformation approach for parallel recursive and adaptive filtering and svd algorithms

Ma, J., Parhi, K. K. & Deprettere, E. F., Feb 1 2001, In : IEEE Transactions on Signal Processing. 49, 2, p. 424-437 14 p.

Research output: Contribution to journalArticle

Adaptive filtering
Parallel architectures
Singular value decomposition
Digital filters
Adaptive filters
1 Citation (Scopus)
multipliers
very large scale integration
Electric power utilization
Networks (circuits)
logic
7 Citations (Scopus)

Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders

Wang, Z., Suzuki, H. & Parhi, K. K., Dec 1 2001, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 29, 3, p. 209-221 13 p.

Research output: Contribution to journalArticle

Decoding
Hardware
Degradation
Normalization
Power Consumption
5 Citations (Scopus)
Adaptive filters
Decomposition
Throughput
Communication
Code division multiple access
75 Citations (Scopus)

Low-power 4-2 and 5-2 compressors

Prasad, K. & Parhi, K. K., Jan 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 129-133 5 p.

Research output: Contribution to journalArticle

Compressors
Networks (circuits)
Electric power utilization
1 Citation (Scopus)
Electric power utilization
Computational complexity
Planning
2 Citations (Scopus)

Novel low-power shared division and square-root architecture using the GST algorithm

Kuhlmann, M. & Parhi, K. K., Jan 1 2001, In : VLSI Design. 12, 3, p. 365-376 12 p.

Research output: Contribution to journalArticle

Electric power utilization
3 Citations (Scopus)

Sign extension reduction by propagated-carry selection

Kim, S. M., Chung, J. G. & Parhi, K. K., Dec 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 134-138 5 p.

Research output: Contribution to journalArticle

Electric power utilization
Hardware
79 Citations (Scopus)

Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials

Zhang, T. & Parhi, K. K., Jul 1 2001, In : IEEE Transactions on Computers. 50, 7, p. 734-749 16 p.

Research output: Contribution to journalArticle

Irreducible polynomial
Multiplier
Polynomials
Matrix Product
Standard Basis
10 Citations (Scopus)

Vector processing of wavelet coefficients for robust image denoising

Zervakis, M. E., Sundararajan, V. & Parhi, K. K., May 1 2001, In : Image and Vision Computing. 19, 7, p. 435-450 16 p.

Research output: Contribution to journalArticle

Image denoising
Impulse noise
Processing
Contamination
Hardware
2000
49 Citations (Scopus)

2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

Chang, Y. N., Suzuki, H. & Parhi, K. K., Jan 1 2000, In : IEEE Journal of Solid-State Circuits. 35, 6, p. 826-834 9 p.

Research output: Contribution to journalArticle

Data storage equipment
Transistors
Logic circuits
Multiplexing
Code division multiple access
2 Citations (Scopus)

Angle-constrained IIR filter pipelining for reduced coefficient sensitivities

Chung, J. G., Kim, H. & Parhi, K. K., Dec 3 2000, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47, 6, p. 555-559 5 p.

Research output: Contribution to journalArticle

IIR filters
Poles
Poles and zeros
Hardware
3 Citations (Scopus)

Digit-serial fixed coefficient complex number multiplier-accumulator on FPGAs

Sansaloni, T., Valls, J. & Parhi, K. K., Jan 1 2000, In : Proceedings of the Annual IEEE International ASIC Conference and Exhibit. p. 236-240 5 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Networks (circuits)
7 Citations (Scopus)

Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

Ma, J., Parhi, K. K., Hekstra, G. J. & Deprettere, E. F., Sep 1 2000, In : IEEE Transactions on Signal Processing. 48, 9, p. 2712-2716 5 p.

Research output: Contribution to journalArticle

IIR filters
Digital computers
Digital filters
Computer architecture
1 Citation (Scopus)

FPGA-based digit-serial Complex Number Multiplier-Accumulator

Sansaloni, T., Valls, J. & Parhi, K. K., Jan 1 2000, In : Proceedings - IEEE International Symposium on Circuits and Systems. 4, p. IV-585-IV-588

Research output: Contribution to journalArticle

Adders
Field programmable gate arrays (FPGA)
22 Citations (Scopus)

Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

Song, L., Parhi, K. K., Kuroda, I. & Nishitani, T., Jan 1 2000, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8, 2, p. 160-172 13 p.

Research output: Contribution to journalArticle

Scheduling
Compact disk players
Hardware
Software radio
Digital signal processors
15 Citations (Scopus)
Adaptive filters
Beamforming
Decomposition
Systolic arrays
Sonar
3 Citations (Scopus)

High-performance digit-serial complex multiplier

Chang, Y. N. & Parhi, K. K., Dec 3 2000, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47, 6, p. 570-572 3 p.

Research output: Contribution to journalArticle

Numbering systems
Electric wiring
Energy dissipation
Throughput
Hardware
Adaptive filters
Decomposition
Throughput
Hardware
Degradation
3 Citations (Scopus)

Low-memory, fixed-latency Huffman encoder for unbounded-length codes

Freking, R. A. & Parhi, K. K., Dec 1 2000, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 2, p. 1031-1034 4 p.

Research output: Contribution to journalArticle

Data storage equipment
Binary trees
Decoding
Data structures
1 Citation (Scopus)

Low-power correlator

Sahoo, B., Kuhlmann, M. & Parhi, K. K., Jan 1 2000, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 153-155 3 p.

Research output: Contribution to journalArticle

Correlators
Adders
Matched filters
Code division multiple access
Electric potential
1 Citation (Scopus)

MINFLOTRANSIT: min-cost flow based transistor sizing tool

Sundararajan, V., Sapatnekar, S. S. & Parhi, K. K., Jan 1 2000, In : Proceedings - Design Automation Conference. p. 649-654 6 p.

Research output: Contribution to journalArticle

Transistors
Networks (circuits)
Costs
Combinatorial circuits
Wire
4 Citations (Scopus)
Public key cryptography
Numbering systems
1 Citation (Scopus)
Adders
Mathematical operators
5 Citations (Scopus)

Pipelined CORDIC-based cascade orthogonal IIR digital filters

Ma, J., Parhi, K. K. & Deprettere, E. F., Nov 1 2000, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47, 11, p. 1238-1253 16 p.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Transfer functions
Decomposition
Topology
3 Citations (Scopus)
Pipelining
Adaptive Filter
Adaptive filters
Folding
Communication
4 Citations (Scopus)

Power Estimation of Digital Data Paths Using HEAT

Satyanarayana, J. H. & Parhi, K. K., Apr 1 2000, In : IEEE Design and Test of Computers. 17, 2, p. 101-110 10 p.

Research output: Contribution to journalArticle

Electric power utilization
8 Citations (Scopus)

Reducing bus transition activity by limited weight coding with codeword slimming

Sundararajan, V. & Parhi, K. K., Jan 1 2000, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 13-16 4 p.

Research output: Contribution to journalArticle

Redundancy
Energy dissipation
Energy efficiency
Capacitance
Costs
4 Citations (Scopus)
Scalability
Feedback
Parallel processing systems
Degradation
21 Citations (Scopus)

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Satyanarayana, J. H. & Parhi, K. K., Jan 1 2000, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8, 2, p. 148-159 12 p.

Research output: Contribution to journalArticle

Digital circuits
Autocorrelation
Statistics
Networks (circuits)
1999
35 Citations (Scopus)

Efficient crosstalk estimation

Kuhlmann, M., Sapatnekar, S. S. & Parhi, K. K., Dec 1 1999, In : Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. p. 266-272 7 p.

Research output: Contribution to journalArticle

Crosstalk
Capacitance
Wire
SPICE
Networks (circuits)
13 Citations (Scopus)

Efficient FFT implementation using digit-serial arithmetic

Chang, Y. N. & Parhi, K. K., Dec 1 1999, In : IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. p. 645-653 9 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
ROM
Computer hardware
Redundancy
Pipelines
17 Citations (Scopus)

High-speed CORDIC algorithm and architecture for DSP applications

Kuhlmann, M. & Parhi, K. K., Dec 1 1999, In : IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. p. 732-741 10 p.

Research output: Contribution to journalArticle

Adders
Clocks
Electric delay lines
Degrees of freedom (mechanics)
Pipelines
16 Citations (Scopus)

Low-energy CSMT carry generators and binary adders

Parhi, K. K., Dec 1 1999, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 7, 4, p. 450-462 13 p.

Research output: Contribution to journalArticle

Adders
Electric power utilization
Energy utilization
67 Citations (Scopus)
VLSI circuits
Threshold voltage
Electric power utilization
Transistors
Electric potential
7 Citations (Scopus)
Networks (circuits)
Polynomials
Clocks