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Research Output 1986 2019

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Article
2006
73 Citations (Scopus)

On the Optimum Constructions of Composite Field for the AES Algorithm

Zhang, X. & Parhi, K. K., Jan 1 2006, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 53, 10, p. 1153-1157 5 p.

Research output: Contribution to journalArticle

Cryptography
Composite materials
Polynomials
Computer hardware
11 Citations (Scopus)

Parallelization of context-based adaptive binary arithmetic coders

Lin, J. H. & Parhi, K. K., Oct 1 2006, In : IEEE Transactions on Signal Processing. 54, 10, p. 3702-3711 10 p.

Research output: Contribution to journalArticle

Table lookup
Image compression
Decoding
Throughput
Hardware
2005
42 Citations (Scopus)

A Novel Systolic Array Structure for DCT

Cheng, C. & Parhi, K. K., Jul 5 2005, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 52, 7, p. 366-369 4 p.

Research output: Contribution to journalArticle

Systolic arrays
Discrete cosine transforms
Convolution
VLSI circuits
38 Citations (Scopus)
Decision feedback equalizers
Pipelines
Throughput
30 Citations (Scopus)

Fast factorization architecture in soft-decision Reed-Solomon decoding

Zhang, X. & Parhi, K. K., Apr 1 2005, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13, 4, p. 413-426 14 p.

Research output: Contribution to journalArticle

Factorization
Reed-Solomon codes
Decoding
Communication systems
Computer systems
42 Citations (Scopus)

High-speed architectures for parallel long BCH encoders

Zhang, X. & Parhi, K. K., Jul 1 2005, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13, 7, p. 872-877 6 p.

Research output: Contribution to journalArticle

Codes (standards)
Digital video broadcasting (DVB)
Reed-Solomon codes
Shift registers
Optical communication
2 Citations (Scopus)
Parity
Decoding
Hamming Code
Coding Gain
Memory Management
3 Citations (Scopus)

VLSI architectures for stereoscopic video disparity matching and object extraction

Lin, J. H. & Parhi, K. K., Dec 1 2005, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 2373-2376 4 p., 1465102.

Research output: Contribution to journalArticle

Computer vision
Computational complexity
Color
Hardware
2004
Networks (circuits)
Polynomials
Clocks
27 Citations (Scopus)
Convolutional codes
Decoding
Communication systems
21 Citations (Scopus)
Reed-Solomon codes
Parallel architectures
Optical communication
Communication systems
Hardware
1 Citation (Scopus)
Ethernet
Trellis codes
Modulation
Copper
Pulse amplitude modulation
10 Citations (Scopus)

Design and implementation of multi-band pulsed-OFDM system for wireless personal area networks

Saberinia, E., Tang, J., Tewfik, A. H. & Parhi, K. K., Aug 30 2004, In : IEEE International Conference on Communications. 2, p. 862-866 5 p.

Research output: Contribution to journalArticle

Personal communication systems
Orthogonal frequency division multiplexing
Fast Fourier transforms
Convolutional codes
Multipath propagation
121 Citations (Scopus)

Design of low-error fixed-width modified booth multiplier

Cho, K. J., Lee, K. C., Chung, J. G. & Parhi, K. K., May 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 5, p. 522-531 10 p.

Research output: Contribution to journalArticle

Error compensation
Electric power utilization
Hardware
Networks (circuits)
68 Citations (Scopus)
FIR filters
Convolution
Hardware
Costs
Ultra-wideband (UWB)
Decoding
Maximum likelihood
Personal communication systems
Bit error rate
283 Citations (Scopus)

High-speed VLSI architectures for the AES algorithm

Zhang, X. & Parhi, K. K., Sep 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 9, p. 957-967 11 p.

Research output: Contribution to journalArticle

Cryptography
Throughput
Computer hardware
Field programmable gate arrays (FPGA)
Composite materials
2 Citations (Scopus)
Ethernet
decoders
decoding
Decoding
Modulation
59 Citations (Scopus)

Joint (3, k)-Regular LDPC Code and Decoder/Encoder Design

Zhang, T. & Parhi, K. K., Apr 1 2004, In : IEEE Transactions on Signal Processing. 52, 4, p. 1065-1079 15 p.

Research output: Contribution to journalArticle

Hardware
Decoding
13 Citations (Scopus)

Low-latency architectures for high-throughput rate Viterbi decoders

Kong, J. J. & Parhi, K. K., Jun 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 6, p. 642-651 10 p.

Research output: Contribution to journalArticle

Decoding
Throughput
Convolutional codes
Hardware
2 Citations (Scopus)
Convolutional codes
Decoding
Communication systems
2 Citations (Scopus)

On the better protection of short-frame turbo codes

Chi, Z., Wang, Z. & Parhi, K. K., Sep 1 2004, In : IEEE Transactions on Communications. 52, 9, p. 1435-1439 5 p.

Research output: Contribution to journalArticle

Turbo codes
Trellis codes
Iterative decoding
Redundancy
Decoding
17 Citations (Scopus)

On The Performance/Complexity Tradeoff in Block Turbo Decoder Design

Chi, Z., Song, L. & Parhi, K. K., Feb 1 2004, In : IEEE Transactions on Communications. 52, 2, p. 173-175 3 p.

Research output: Contribution to journalArticle

VLSI circuits
Decoding
122 Citations (Scopus)

Overlapped message passing for quasi-cyclic low-density parity check codes

Chen, Y. & Parhi, K. K., Jun 1 2004, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 51, 6, p. 1106-1113 8 p.

Research output: Contribution to journalArticle

Message passing
Decoding
Throughput
Data storage equipment
Scheduling algorithms
27 Citations (Scopus)

Parallel turbo decoding

Zhang, Y. & Parhi, K. K., Sep 7 2004, In : Proceedings - IEEE International Symposium on Circuits and Systems. 2

Research output: Contribution to journalArticle

Turbo codes
Decoding
Parallel architectures
7 Citations (Scopus)

Pipelined CORDIC-based state-space orthogonal recursive digital filters using matrix look-ahead

Ma, J. & Parhi, K. K., Jul 1 2004, In : IEEE Transactions on Signal Processing. 52, 7, p. 2102-2119 18 p.

Research output: Contribution to journalArticle

Digital computers
Digital filters
Topology
Telephone systems
IIR filters
7 Citations (Scopus)
Decision feedback equalizers
Throughput
Pipelines
high speed
9 Citations (Scopus)

Reduced complexity sphere decoding and application to interfering IEEE 802.15.3a piconets

Tang, J., Tewfik, A. H. & Parhi, K. K., Aug 31 2004, In : IEEE International Conference on Communications. 5, p. 2864-2868 5 p.

Research output: Contribution to journalArticle

Decoding
Maximum likelihood
Personal communication systems
Bit error rate
Signal to noise ratio
57 Citations (Scopus)

Small area parallel chien search architectures for long BCH codes

Chen, Y. & Parhi, K. K., May 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 5, p. 545-549 5 p.

Research output: Contribution to journalArticle

Hardware
2003

A low power correlator for CDMA wireless systems

Sahoo, B. & Parhi, K. K., Aug 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 35, 1, p. 105-112 8 p.

Research output: Contribution to journalArticle

Correlators
Ripple
Correlator
Code Division multiple Access
Code division multiple access
63 Citations (Scopus)

An efficient pipelined FFT architecture

Chang, Y. N. & Parhi, K. K., Jun 1 2003, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 50, 6, p. 322-325 4 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
ROM
Electric commutators
Computer hardware
Redundancy
22 Citations (Scopus)

An FPGA implementation of (3,6)-regular low-density parity-check code decoder

Zhang, T. & Parhi, K. K., May 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 6, p. 530-542 13 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Hardware
Decoding
Throughput
Parallel architectures
3 Citations (Scopus)

Digit-serial complex-number multipliers on FPGAs

Sansaloni, T., Valls, J. & Parhi, K. K., Jan 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 33, 1-2, p. 105-115 11 p.

Research output: Contribution to journalArticle

Adders
Complex number
Digit
Field Programmable Gate Array
Multiplier
37 Citations (Scopus)

High performance, high throughput turbo/SOVA decoder design

Wang, Z. & Parhi, K. K., Apr 1 2003, In : IEEE Transactions on Communications. 51, 4, p. 570-579 10 p.

Research output: Contribution to journalArticle

Viterbi algorithm
Parallel architectures
Throughput
Bit error rate
Hardware
5 Citations (Scopus)

Interleaved convolutional code and its Viterbi decoder architecture

Kong, J. J. & Parhi, K. K., Dec 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 13, p. 1328-1334 7 p.

Research output: Contribution to journalArticle

Convolutional codes
Data storage equipment
Parallel architectures
Decoding
Clocks

Low-complexity decoding of block turbo-coded system with antenna diversity

Chen, Y. & Parhi, K. K., Dec 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 13, p. 1335-1345 11 p.

Research output: Contribution to journalArticle

Decoding
Antennas
Block codes
Bit error rate
Degradation
40 Citations (Scopus)

Low Error Fixed-Width CSD Multiplier with Efficient Sign Extension

Kim, S. M., Chung, J. G. & Parhi, K. K., Dec 1 2003, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 50, 12, p. 984-993 10 p.

Research output: Contribution to journalArticle

Error compensation
Hardware
3 Citations (Scopus)
Power spectrum
Ultra-wideband (UWB)
Communication
Frequency hopping
Communication systems
1 Citation (Scopus)

Relaxed annihilation-reordering look-ahead QRD-RLS adaptive filters

Gao, L., Parhi, K. K. & Ma, J., Sep 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 35, 2, p. 119-135 17 p.

Research output: Contribution to journalArticle

Adaptive Filter
Look-ahead
Reordering
Adaptive filters
Annihilation
4 Citations (Scopus)

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

Sundararajan, V. & Parhi, K. K., Jul 1 2003, In : IEEE Transactions on Signal Processing. 51, 7, p. 1954-1965 12 p.

Research output: Contribution to journalArticle

Data flow graphs
Data storage equipment
IIR filters
Signal analysis
Wavelet transforms
2002
46 Citations (Scopus)

Area-efficient high-speed decoding schemes for turbo decoders

Wang, Z., Chi, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 6, p. 902-912 11 p.

Research output: Contribution to journalArticle

Decoding
Throughput
Iterative decoding
Pipelines
Degradation
13 Citations (Scopus)

Design of low error CSD fixed-width multiplier

Kim, S. M., Chung, J. G. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1

Research output: Contribution to journalArticle

Error compensation
Logic gates
Networks (circuits)
3 Citations (Scopus)

Energy efficient signaling in deep-submicron technology

Dhaou, I. B., Parhi, K. K. & Tenhunen, H., Jan 1 2002, In : VLSI Design. 15, 3, p. 563-586 24 p.

Research output: Contribution to journalArticle

Capacitance
Crosstalk
Wire
Electric power utilization
Electric potential
52 Citations (Scopus)

Evaluation of CORDIC algorithms for FPGA design

Valls, J., Kuhlmann, M. & Parhi, K. K., Jan 1 2002, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 32, 3, p. 207-222 16 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
FPGA Implementation
Evaluation
Operator
52 Citations (Scopus)

Fast and exact transistor sizing based on iterative relaxation

Sundararajan, V., Sapatnekar, S. S. & Parhi, K. K., May 1 2002, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21, 5, p. 568-581 14 p.

Research output: Contribution to journalArticle

Transistors
Networks (circuits)
Combinatorial circuits
Costs
Wire
39 Citations (Scopus)

Frequency spectrum based low-area low-power parallel FIR filter design

Chung, J. G. & Parhi, K. K., Sep 1 2002, In : Eurasip Journal on Applied Signal Processing. 2002, 9, p. 944-953 10 p.

Research output: Contribution to journalArticle

FIR filters
Hardware
Adders
Digital filters
Costs
10 Citations (Scopus)

High-speed add-compare-select units using locally self-resetting CMOS

Jung, G., Kong, J. J., Sobelman, G. E. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 889-892 4 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
9 Citations (Scopus)

High speed VLSI architecture design for block turbo decoder

Chi, Z. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 901-904 4 p.

Research output: Contribution to journalArticle

Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
83 Citations (Scopus)

Implementation approaches for the advanced encryption standard algorithm

Xinmiao, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Circuits and Systems Magazine. 2, 4, p. 24-46 23 p.

Research output: Contribution to journalArticle

Cryptography
Computer hardware
Feedback
Processing