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Research Output 1986 2019

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8 Citations (Scopus)

100 MHz pipelined RLS adaptive filter

Raghunath, K. J. & Parhi, K. K., Jan 1 1995, In : ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. 5, p. 3187-3190 4 p.

Research output: Contribution to journalArticle

Adaptive filters
Numbering systems
Application specific integrated circuits
49 Citations (Scopus)

2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

Chang, Y. N., Suzuki, H. & Parhi, K. K., Jan 1 2000, In : IEEE Journal of Solid-State Circuits. 35, 6, p. 826-834 9 p.

Research output: Contribution to journalArticle

Data storage equipment
Transistors
Logic circuits
Multiplexing
Code division multiple access
3 Citations (Scopus)

Abnormal neural oscillations in schizophrenia assessed by spectral power ratio of MEG during word processing

Xu, T., Stephane, M. & Parhi, K. K., Nov 1 2016, In : IEEE Transactions on Neural Systems and Rehabilitation Engineering. 24, 11, p. 1148-1158 11 p., 7448911.

Research output: Contribution to journalArticle

Magnetoencephalography
Word processing
Word Processing
Schizophrenia
Frequency bands
1 Citation (Scopus)

A C-Testable Carry-Free Divider

Srinivas, H. R., Vinnakota, B. & Parhi, K. K., Jan 1 1994, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2, 4, p. 472-488 17 p.

Research output: Contribution to journalArticle

Adders
Testing
Hardware
26 Citations (Scopus)

A Fast Radix-4 Division Algorithm and its Architecture

Srinivas, H. R. & Parhi, K. K., Jan 1 1995, In : IEEE Transactions on Computers. 44, 6, p. 826-831 6 p.

Research output: Contribution to journalArticle

Digit
Division
Remainder
Quotient
Partial
41 Citations (Scopus)

A Fast VLSI Adder Architecture

Srinivas, H. R. & Parhi, K. K., May 1992, In : IEEE Journal of Solid-State Circuits. 27, 5, p. 761-767 7 p.

Research output: Contribution to journalArticle

Adders
2 Citations (Scopus)
Counting
Synthesis
Costs
Integer Linear Programming
Converter
112 Citations (Scopus)

Algorithm Transformation Techniques for Concurrent Processors

Parhi, K. K., Jan 1 1989, In : Proceedings of the IEEE. 77, 12, p. 1879-1895 17 p.

Research output: Contribution to journalArticle

Supercomputers
VLSI circuits
Application specific integrated circuits
15 Citations (Scopus)

A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet

Cohen, A. E. & Parhi, K. K., Oct 9 2009, In : IEEE Transactions on Signal Processing. 57, 10, p. 4085-4094 10 p.

Research output: Contribution to journalArticle

Ethernet
ROM
Transceivers
Cables
Electric power utilization
6 Citations (Scopus)
Seizures
Computational complexity
Databases
Sensitivity and Specificity
Equipment and Supplies

A low power correlator for CDMA wireless systems

Sahoo, B. & Parhi, K. K., Aug 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 35, 1, p. 105-112 8 p.

Research output: Contribution to journalArticle

Correlators
Ripple
Correlator
Code Division multiple Access
Code division multiple access
17 Citations (Scopus)

An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip

Hatamian, M. & Parhi, K. K., Jan 1 1992, In : IEEE Journal of Solid-State Circuits. 27, 2, p. 175-183 9 p.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Clocks
FIR filters
Networks (circuits)
63 Citations (Scopus)

An efficient pipelined FFT architecture

Chang, Y. N. & Parhi, K. K., Jun 1 2003, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 50, 6, p. 322-325 4 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
ROM
Electric commutators
Computer hardware
Redundancy
10 Citations (Scopus)

A network-efficient nonbinary QC-LDPC decoder architecture

Zhang, C. & Parhi, K. K., Jan 23 2012, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 6, p. 1359-1371 13 p., 6132390.

Research output: Contribution to journalArticle

Switches
Decoding
Clocks
Throughput
Hardware
Networks (circuits)
Polynomials
Clocks
22 Citations (Scopus)

An FPGA implementation of (3,6)-regular low-density parity-check code decoder

Zhang, T. & Parhi, K. K., May 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 6, p. 530-542 13 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Hardware
Decoding
Throughput
Parallel architectures
2 Citations (Scopus)

Angle-constrained IIR filter pipelining for reduced coefficient sensitivities

Chung, J. G., Kim, H. & Parhi, K., Dec 3 2000, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47, 6, p. 555-559 5 p.

Research output: Contribution to journalArticle

IIR filters
Poles
Poles and zeros
Hardware
27 Citations (Scopus)
Convolutional codes
Decoding
Communication systems
39 Citations (Scopus)

An in-place fft architecture for real-valued signals

Ayinala, M., Lao, Y. & Parhi, K. K., Aug 19 2013, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 60, 10, p. 652-656 5 p., 6576819.

Research output: Contribution to journalArticle

Fast Fourier transforms
Hardware
Flow graphs
Data storage equipment
Processing
42 Citations (Scopus)

A Novel Systolic Array Structure for DCT

Cheng, C. & Parhi, K. K., Jul 5 2005, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 52, 7, p. 366-369 4 p.

Research output: Contribution to journalArticle

Systolic arrays
Discrete cosine transforms
Convolution
VLSI circuits
2 Citations (Scopus)
Speech coding
Degradation
Integrated circuits
Signal to noise ratio
Hardware
16 Citations (Scopus)

A Pipelined Adaptive Lattice Filter Architecture

Shanbhag, N. R. & Parhi, K. K., Jan 1 1993, In : IEEE Transactions on Signal Processing. 41, 5, p. 1925-1939 15 p.

Research output: Contribution to journalArticle

Differential pulse code modulation
Adaptive filters
Image compression
Pipelines
Hardware
87 Citations (Scopus)

A pipelined FFT architecture for real-valued signals

Garrido, M., Parhi, K. K. & Grajal, J., Dec 2009, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 56, 12, p. 2634-2643 10 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
Hardware
Throughput
Decomposition
Geometry
15 Citations (Scopus)

Approaches to low-power implementations of DSP systems

Parhi, K. K., Oct 1 2001, In : IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 48, 10, p. 1214-1224 11 p.

Research output: Contribution to journalArticle

Electric power utilization
FIR filters
Equalizers
Fast Fourier transforms
Digital subscriber lines
7 Citations (Scopus)

ARCHITECTURE CONSIDERATIONS FOR HIGH SPEED RECURSIVE FILTERING.

Parhi, K. K., Chen, W. L. & Messerschmitt, D. G., Jan 1 1987, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 374-377 4 p.

Research output: Contribution to journalArticle

Digital filters
Pipelines
Sampling
Decomposition

Architecture optimization and performance comparison of nonce-misuse-resistant authenticated encryption algorithms

Koteshwara, S., Das, A. & Parhi, K. K., May 1 2019, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 5, p. 1053-1066 14 p., 8648246.

Research output: Contribution to journalArticle

Cryptography
Application specific integrated circuits
Field programmable gate arrays (FPGA)
12 Citations (Scopus)

Architecture optimizations for the RSA public key cryptosystem: A tutorial

Cohen, A. E. & Parhi, K. K., Dec 1 2011, In : IEEE Circuits and Systems Magazine. 11, 4, p. 24-34 11 p., 6035849.

Research output: Contribution to journalArticle

Cryptography
Particle accelerators
Virtual private networks
Systolic arrays
Textbooks
10 Citations (Scopus)
Discrete wavelet transforms
Digital filters
Adders
FIR filters
Processing
17 Citations (Scopus)

Architectures for Recursive Digital Filters Using Stochastic Computing

Liu, Y. & Parhi, K. K., Jul 15 2016, In : IEEE Transactions on Signal Processing. 64, 14, p. 3705-3718 14 p., 7450670.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Feedback
Hardware
Logic gates
46 Citations (Scopus)

Area-efficient high-speed decoding schemes for turbo decoders

Wang, Z., Chi, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 6, p. 902-912 11 p.

Research output: Contribution to journalArticle

Decoding
Throughput
Iterative decoding
Pipelines
Degradation
21 Citations (Scopus)
Reed-Solomon codes
Parallel architectures
Optical communication
Communication systems
Hardware
5 Citations (Scopus)

A Serial Commutator Fast Fourier Architecture for Real-Valued Signals

Garrido, M., Unnikrishnan, N. K. & Parhi, K. K., Nov 1 2018, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 65, 11, p. 1693-1697 5 p., 8039527.

Research output: Contribution to journalArticle

Electric commutators
Fast Fourier transforms
Hardware
Adders
Electronic data interchange

A study on the performance, complexity tradeoffs of block turbo decoder design

Chi, Z., Song, L. & Parhi, K. K., Jan 1 2001, In : Materials Research Society Symposium - Proceedings. 626

Research output: Contribution to journalArticle

decoders
tradeoffs
Decoding
decoding
very large scale integration
110 Citations (Scopus)

A systematic approach for design of digit-serial signal processing architectures

Parhi, K. K., Apr 1 1991, In : IEEE transactions on circuits and systems. 38, 4, p. 358-375 18 p.

Research output: Contribution to journalArticle

Signal processing
Clocks
Parallel architectures
Adders
Hardware
12 Citations (Scopus)
Electric power utilization
Binary trees
Heat sinks
2 Citations (Scopus)

A unified adder design

Wang, Y. & Parhi, K. K., Jan 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 177-182 6 p.

Research output: Contribution to journalArticle

Adders
Carry logic
Transistors
11 Citations (Scopus)

A unified algebraic transformation approach for parallel recursive and adaptive filtering and svd algorithms

Ma, J., Parhi, K. K. & Deprettere, E. F., Feb 1 2001, In : IEEE Transactions on Signal Processing. 49, 2, p. 424-437 14 p.

Research output: Contribution to journalArticle

Adaptive filtering
Parallel architectures
Singular value decomposition
Digital filters
Adaptive filters
21 Citations (Scopus)
Macular Edema
Optical tomography
Optical Coherence Tomography
Cysts
Pixels
2 Citations (Scopus)
Detectors
Statistical methods
Jitter
Networks (circuits)
Costs
15 Citations (Scopus)

BLOCK DIGITAL FILTERING VIA INCREMENTAL BLOCK-STATE STRUCTURE.

Parhi, K. K. & Messerschmitt, D. G., Jan 1 1987, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 645-648 4 p.

Research output: Contribution to journalArticle

Digital filters
103 Citations (Scopus)

Blood vessel segmentation of fundus images by major vessel extraction and subimage classification

Roychowdhury, S., Koozekanani, D. & Parhi, K. K., May 1 2015, In : IEEE Journal of Biomedical and Health Informatics. 19, 3, p. 1118-1128 11 p., 6848752.

Research output: Contribution to journalArticle

Binary images
Blood vessels
Blood Vessels
Pixels
Pathology
21 Citations (Scopus)
Digital signal processing
Networks (circuits)

Canonic Composite Length Real-Valued FFT

Lao, Y. & Parhi, K. K., Oct 1 2018, In : Journal of Signal Processing Systems. 90, 10, p. 1401-1414 14 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
Odd
Composite
Fast Fourier transform
Composite materials
2 Citations (Scopus)

Canonic FFT flow graphs for real-valued even/odd symmetric inputs

Lao, Y. & Parhi, K. K., Dec 1 2017, In : Eurasip Journal on Advances in Signal Processing. 2017, 1, 45.

Research output: Contribution to journalArticle

Flow graphs
Fast Fourier transforms
Redundancy
15 Citations (Scopus)

Chemical reaction networks for computing polynomials

Salehi, S. A., Parhi, K. K. & Riedel, M., Jan 1 2017, In : ACS Synthetic Biology. 6, 1, p. 76-83 8 p.

Research output: Contribution to journalArticle

Chemical reactions
Molecular Computers
Polynomials
DNA
Molecules
7 Citations (Scopus)
Person
Error Rate
Biometrics
Fusion reactions
Coefficient
22 Citations (Scopus)
Amplitude modulation
Phase modulation
Equalizers
Transceivers
Hardware
1 Citation (Scopus)
Ethernet
Trellis codes
Modulation
Copper
Pulse amplitude modulation
42 Citations (Scopus)

Computation error analysis in digital signal processing systems with overscaled supply voltage

Liu, Y., Zhang, T. & Parhi, K. K., Apr 1 2010, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 4, p. 517-526 10 p., 5075518.

Research output: Contribution to journalArticle

Digital signal processing
Error analysis
Signal processing
Electric potential
Energy conservation
7 Citations (Scopus)

Computing arithmetic functions using stochastic logic by series expansion

Parhi, K. K. & Liu, Y., Jan 1 2019, In : IEEE Transactions on Emerging Topics in Computing. 7, 1, p. 44-59 16 p., 7593286.

Research output: Contribution to journalArticle

Polynomials
Finite automata
Logic circuits
Factorization
Hardware