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Research Output 1986 2019

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Article
2000
3 Citations (Scopus)

Low-memory, fixed-latency Huffman encoder for unbounded-length codes

Freking, R. A. & Parhi, K. K., Dec 1 2000, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 2, p. 1031-1034 4 p.

Research output: Contribution to journalArticle

Data storage equipment
Binary trees
Decoding
Data structures
1 Citation (Scopus)

Low-power correlator

Sahoo, B., Kuhlmann, M. & Parhi, K. K., Jan 1 2000, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 153-155 3 p.

Research output: Contribution to journalArticle

Correlators
Adders
Matched filters
Code division multiple access
Electric potential
1 Citation (Scopus)
Adders
Mathematical operators
5 Citations (Scopus)

Pipelined CORDIC-based cascade orthogonal IIR digital filters

Ma, J., Parhi, K. K. & Deprettere, E. F., Nov 1 2000, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47, 11, p. 1238-1253 16 p.

Research output: Contribution to journalArticle

IIR filters
Digital filters
Transfer functions
Decomposition
Topology
3 Citations (Scopus)
Pipelining
Adaptive Filter
Adaptive filters
Folding
Communication
4 Citations (Scopus)

Power Estimation of Digital Data Paths Using HEAT

Satyanarayana, J. H. & Parhi, K. K., Apr 1 2000, In : IEEE Design and Test of Computers. 17, 2, p. 101-110 10 p.

Research output: Contribution to journalArticle

Electric power utilization
21 Citations (Scopus)

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Satyanarayana, J. H. & Parhi, K. K., Jan 1 2000, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8, 2, p. 148-159 12 p.

Research output: Contribution to journalArticle

Digital circuits
Autocorrelation
Statistics
Networks (circuits)
2001
15 Citations (Scopus)

Approaches to low-power implementations of DSP systems

Parhi, K. K., Oct 1 2001, In : IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 48, 10, p. 1214-1224 11 p.

Research output: Contribution to journalArticle

Electric power utilization
FIR filters
Equalizers
Fast Fourier transforms
Digital subscriber lines
2 Citations (Scopus)

A unified adder design

Wang, Y. & Parhi, K. K., Jan 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 177-182 6 p.

Research output: Contribution to journalArticle

Adders
Carry logic
Transistors
11 Citations (Scopus)

A unified algebraic transformation approach for parallel recursive and adaptive filtering and svd algorithms

Ma, J., Parhi, K. K. & Deprettere, E. F., Feb 1 2001, In : IEEE Transactions on Signal Processing. 49, 2, p. 424-437 14 p.

Research output: Contribution to journalArticle

Adaptive filtering
Parallel architectures
Singular value decomposition
Digital filters
Adaptive filters
1 Citation (Scopus)
multipliers
very large scale integration
Electric power utilization
Networks (circuits)
logic
7 Citations (Scopus)

Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders

Wang, Z., Suzuki, H. & Parhi, K. K., Dec 1 2001, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 29, 3, p. 209-221 13 p.

Research output: Contribution to journalArticle

Decoding
Hardware
Degradation
Normalization
Power Consumption
5 Citations (Scopus)
Adaptive filters
Decomposition
Throughput
Communication
Code division multiple access
75 Citations (Scopus)

Low-power 4-2 and 5-2 compressors

Prasad, K. & Parhi, K. K., Jan 1 2001, In : Conference Record of the Asilomar Conference on Signals, Systems and Computers. 1, p. 129-133 5 p.

Research output: Contribution to journalArticle

Compressors
Networks (circuits)
Electric power utilization
2 Citations (Scopus)

Novel low-power shared division and square-root architecture using the GST algorithm

Kuhlmann, M. & Parhi, K. K., Jan 1 2001, In : VLSI Design. 12, 3, p. 365-376 12 p.

Research output: Contribution to journalArticle

Electric power utilization
79 Citations (Scopus)

Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials

Zhang, T. & Parhi, K. K., Jul 1 2001, In : IEEE Transactions on Computers. 50, 7, p. 734-749 16 p.

Research output: Contribution to journalArticle

Irreducible polynomial
Multiplier
Polynomials
Matrix Product
Standard Basis
10 Citations (Scopus)

Vector processing of wavelet coefficients for robust image denoising

Zervakis, M. E., Sundararajan, V. & Parhi, K. K., May 1 2001, In : Image and Vision Computing. 19, 7, p. 435-450 16 p.

Research output: Contribution to journalArticle

Image denoising
Impulse noise
Processing
Contamination
Hardware
2002
46 Citations (Scopus)

Area-efficient high-speed decoding schemes for turbo decoders

Wang, Z., Chi, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 6, p. 902-912 11 p.

Research output: Contribution to journalArticle

Decoding
Throughput
Iterative decoding
Pipelines
Degradation
13 Citations (Scopus)

Design of low error CSD fixed-width multiplier

Kim, S. M., Chung, J. G. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1

Research output: Contribution to journalArticle

Error compensation
Logic gates
Networks (circuits)
3 Citations (Scopus)

Energy efficient signaling in deep-submicron technology

Dhaou, I. B., Parhi, K. K. & Tenhunen, H., Jan 1 2002, In : VLSI Design. 15, 3, p. 563-586 24 p.

Research output: Contribution to journalArticle

Capacitance
Crosstalk
Wire
Electric power utilization
Electric potential
52 Citations (Scopus)

Evaluation of CORDIC algorithms for FPGA design

Valls, J., Kuhlmann, M. & Parhi, K. K., Nov 2002, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 32, 3, p. 207-222 16 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
FPGA Implementation
Evaluation
Operator
52 Citations (Scopus)

Fast and exact transistor sizing based on iterative relaxation

Sundararajan, V., Sapatnekar, S. S. & Parhi, K. K., May 1 2002, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21, 5, p. 568-581 14 p.

Research output: Contribution to journalArticle

Transistors
Networks (circuits)
Combinatorial circuits
Costs
Wire
39 Citations (Scopus)

Frequency spectrum based low-area low-power parallel FIR filter design

Chung, J. G. & Parhi, K. K., Sep 1 2002, In : Eurasip Journal on Applied Signal Processing. 2002, 9, p. 944-953 10 p.

Research output: Contribution to journalArticle

FIR filters
Hardware
Adders
Digital filters
Costs
10 Citations (Scopus)

High-speed add-compare-select units using locally self-resetting CMOS

Jung, G., Kong, J. J., Sobelman, G. E. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 889-892 4 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
9 Citations (Scopus)

High speed VLSI architecture design for block turbo decoder

Chi, Z. & Parhi, K. K., Jan 1 2002, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 901-904 4 p.

Research output: Contribution to journalArticle

Decoding
Turbo codes
Computer hardware description languages
Bit error rate
Signal to noise ratio
83 Citations (Scopus)

Implementation approaches for the advanced encryption standard algorithm

Xinmiao, Z. & Parhi, K. K., Dec 1 2002, In : IEEE Circuits and Systems Magazine. 2, 4, p. 24-46 23 p.

Research output: Contribution to journalArticle

Cryptography
Computer hardware
Feedback
Processing
5 Citations (Scopus)
Decoding
Iterative decoding
Signal to noise ratio
Hardware
Degradation
31 Citations (Scopus)

P-CORDIC: A precomputation based rotation CORDIC algorithm

Kuhlmann, M. & Parhi, K. K., Sep 1 2002, In : Eurasip Journal on Applied Signal Processing. 2002, 9, p. 936-943 8 p.

Research output: Contribution to journalArticle

Digital computers
Computer architecture
Degrees of freedom (mechanics)
Pipelines
4 Citations (Scopus)

Performance-scalable array architectures for modular multiplication

Freking, W. L. & Parhi, K. K., Jun 1 2002, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 31, 2, p. 101-116 16 p.

Research output: Contribution to journalArticle

Modular multiplication
Hardware
Systolic arrays
Cryptography
Clocks
2003

A low power correlator for CDMA wireless systems

Sahoo, B. & Parhi, K. K., Aug 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 35, 1, p. 105-112 8 p.

Research output: Contribution to journalArticle

Correlators
Ripple
Correlator
Code Division multiple Access
Code division multiple access
63 Citations (Scopus)

An efficient pipelined FFT architecture

Chang, Y. N. & Parhi, K. K., Jun 1 2003, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 50, 6, p. 322-325 4 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
ROM
Electric commutators
Computer hardware
Redundancy
22 Citations (Scopus)

An FPGA implementation of (3,6)-regular low-density parity-check code decoder

Zhang, T. & Parhi, K. K., May 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 6, p. 530-542 13 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Hardware
Decoding
Throughput
Parallel architectures
3 Citations (Scopus)

Digit-serial complex-number multipliers on FPGAs

Sansaloni, T., Valls, J. & Parhi, K. K., Jan 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 33, 1-2, p. 105-115 11 p.

Research output: Contribution to journalArticle

Adders
Complex number
Digit
Field Programmable Gate Array
Multiplier
37 Citations (Scopus)

High performance, high throughput turbo/SOVA decoder design

Wang, Z. & Parhi, K. K., Apr 1 2003, In : IEEE Transactions on Communications. 51, 4, p. 570-579 10 p.

Research output: Contribution to journalArticle

Viterbi algorithm
Parallel architectures
Throughput
Bit error rate
Hardware
5 Citations (Scopus)

Interleaved convolutional code and its Viterbi decoder architecture

Kong, J. J. & Parhi, K. K., Dec 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 13, p. 1328-1334 7 p.

Research output: Contribution to journalArticle

Convolutional codes
Data storage equipment
Parallel architectures
Decoding
Clocks

Low-complexity decoding of block turbo-coded system with antenna diversity

Chen, Y. & Parhi, K. K., Dec 1 2003, In : Eurasip Journal on Applied Signal Processing. 2003, 13, p. 1335-1345 11 p.

Research output: Contribution to journalArticle

Decoding
Antennas
Block codes
Bit error rate
Degradation
40 Citations (Scopus)

Low Error Fixed-Width CSD Multiplier with Efficient Sign Extension

Kim, S. M., Chung, J. G. & Parhi, K. K., Dec 1 2003, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 50, 12, p. 984-993 10 p.

Research output: Contribution to journalArticle

Error compensation
Hardware
1 Citation (Scopus)

Relaxed annihilation-reordering look-ahead QRD-RLS adaptive filters

Gao, L., Parhi, K. K. & Ma, J., Sep 1 2003, In : Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 35, 2, p. 119-135 17 p.

Research output: Contribution to journalArticle

Adaptive Filter
Look-ahead
Reordering
Adaptive filters
Annihilation
4 Citations (Scopus)

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

Sundararajan, V. & Parhi, K. K., Jul 1 2003, In : IEEE Transactions on Signal Processing. 51, 7, p. 1954-1965 12 p.

Research output: Contribution to journalArticle

Data flow graphs
Data storage equipment
IIR filters
Signal analysis
Wavelet transforms
2004
Networks (circuits)
Polynomials
Clocks
27 Citations (Scopus)
Convolutional codes
Decoding
Communication systems
1 Citation (Scopus)
Ethernet
Trellis codes
Modulation
Copper
Pulse amplitude modulation
10 Citations (Scopus)

Design and implementation of multi-band pulsed-OFDM system for wireless personal area networks

Saberinia, E., Tang, J., Tewfik, A. H. & Parhi, K. K., Aug 30 2004, In : IEEE International Conference on Communications. 2, p. 862-866 5 p.

Research output: Contribution to journalArticle

Personal communication systems
Orthogonal frequency division multiplexing
Fast Fourier transforms
Convolutional codes
Multipath propagation
121 Citations (Scopus)

Design of low-error fixed-width modified booth multiplier

Cho, K. J., Lee, K. C., Chung, J. G. & Parhi, K. K., May 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 5, p. 522-531 10 p.

Research output: Contribution to journalArticle

Error compensation
Electric power utilization
Hardware
Networks (circuits)
68 Citations (Scopus)
FIR filters
Convolution
Hardware
Costs
Ultra-wideband (UWB)
Decoding
Maximum likelihood
Personal communication systems
Bit error rate
283 Citations (Scopus)

High-speed VLSI architectures for the AES algorithm

Zhang, X. & Parhi, K. K., Sep 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 9, p. 957-967 11 p.

Research output: Contribution to journalArticle

Cryptography
Throughput
Computer hardware
Field programmable gate arrays (FPGA)
Composite materials
59 Citations (Scopus)

Joint (3, k)-Regular LDPC Code and Decoder/Encoder Design

Zhang, T. & Parhi, K. K., Apr 1 2004, In : IEEE Transactions on Signal Processing. 52, 4, p. 1065-1079 15 p.

Research output: Contribution to journalArticle

Hardware
Decoding
13 Citations (Scopus)

Low-latency architectures for high-throughput rate Viterbi decoders

Kong, J. J. & Parhi, K. K., Jun 1 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 6, p. 642-651 10 p.

Research output: Contribution to journalArticle

Decoding
Throughput
Convolutional codes
Hardware