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  • 11 Similar Profiles
Networks (circuits) Engineering & Materials Science
Static random access storage Engineering & Materials Science
Electric potential Engineering & Materials Science
Transistors Engineering & Materials Science
Dynamic random access storage Engineering & Materials Science
Leakage currents Engineering & Materials Science
Degradation Engineering & Materials Science
Threshold voltage Engineering & Materials Science

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Projects 2007 2022

Research Output 2002 2018

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer

Chiu, P. W., Kundu, S., Tang, Q. & Kim, C. H. Apr 1 2018 In : IEEE Journal of Solid-State Circuits. 53, 4, p. 1203-1213 11 p.

Research output: Contribution to journalArticle

Decision feedback equalizers
Bit error rate
Binary sequences
Equalizers
Energy efficiency

A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning

Kundu, S., Liu, M., Wong, R., Wen, S. J. & Kim, C. H. Mar 8 2018 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 61, p. 308-310 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Capacitors
Sampling
Electric potential
Electric power utilization
Response time (computer systems)

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Park, G., Kim, M., Kim, C. H., Kim, B. & Reddy, V. May 25 2018 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March, p. 5C.21-5C.26

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase locked loops
Phase noise
Degradation
Networks (circuits)
Monitoring

An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

Kumar, S., Cho, M., Everson, L., Kim, H., Tang, Q., Mazanec, P., Meinerzhagen, P., Malavasi, A., Lake, D., Tokunaga, C., Khellah, M., Tschanz, J., Borkar, S., De, V. & Kim, C. H. Jan 23 2018 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., p. 39.3.1-39.3.4

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
logic circuits
Logic circuits
readout
Logic gates

Effect of aging on linear and nonlinear MUX PUFs by statistical modeling

Koyily, A., Avvaru, S. V. S., Zhou, C., Kim, C. H. & Parhi, K. K. Feb 20 2018 ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 76-83 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Aging of materials
Authentication
Hardware security
Random variables
Tuning