Projects per year
Fingerprint The Fingerprint is created by mining the titles and abstracts of the person's research outputs and projects/funding awards to create an index of weighted terms from discipline-specific thesauri.
- 11 Similar Profiles
Networks (circuits)
Engineering & Materials Science
Static random access storage
Engineering & Materials Science
Electric potential
Engineering & Materials Science
Transistors
Engineering & Materials Science
Dynamic random access storage
Engineering & Materials Science
Degradation
Engineering & Materials Science
Leakage currents
Engineering & Materials Science
Capacitors
Engineering & Materials Science
Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects 2007 2022
SHF: Medium: Time Based Deep Neural Networks: An Integra
Sapatnekar, S. S., Zhao, Q. & Kim, C. H.
5/1/18 → 4/30/22
Project: Research project
Software
Research
Mitigating Reliability Issues in Analog Circuits
Sapatnekar, S. S. & Kim, C. H.
3/1/17 → 12/31/19
Project: Research project
Analog circuits
Threshold voltage
Networks (circuits)
Research Output 2002 2019
2.5 A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control
Everson, L. R., Sapatnekar, S. S. & Kim, C. H., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 50-52 3 p. 8662455. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Wavefronts
Application specific integrated circuits
Data storage equipment
Pulse shaping
Computer architecture
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology
Kim, M., Kim, J., Park, C., Everson, L. R., Kim, H., Song, S., Lee, S. & Kim, C. H., Jan 16 2019, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 15.4.1-15.4.4 8614599. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
synapses
Flash memory
Voltage control
Neurons
logic
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing
Park, G., Kim, M., Pande, N., Chiu, P. W., Song, J. & Kim, C. H., Apr 1 2019, 2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc., 8780279. (Proceedings of the Custom Integrated Circuits Conference; vol. 2019-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Digital to analog conversion
Networks (circuits)
Testing
Data transfer
Electric potential
2
Citations
(Scopus)
A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer
Kundu, S., Liu, M., Wen, S. J., Wong, R. & Kim, C. H., Jan 1 2019, In : IEEE Journal of Solid-State Circuits. 54, 1, p. 109-120 12 p., 8478195.Research output: Contribution to journal › Article
Sampling
Electric potential
Flip flop circuits
Variable frequency oscillators
Clocks
Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array
Kumar, S., Cho, M., Everson, L. R., Tang, Q., Meinerzhagen, P., Malavasi, A., Lake, D., Tokunaga, C., Khellah, M., Tschanz, J., De, V. & Kim, C. H., Jun 1 2019, In : IEEE Transactions on Nuclear Science. 66, 6, p. 918-925 8 p., 8692625.Research output: Contribution to journal › Article
flip-flops
Flip flop circuits
Neutrons
neutrons
Electric network topology